HW-V5-ML506-UNI-G Xilinx Inc, HW-V5-ML506-UNI-G Datasheet - Page 41

• Manufacturer Part Number: HW-V5-ML506-UNI-G
• Description: EVALUATION PLATFORM VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr
• Type: DSPr

Specifications of HW-V5-ML506-UNI-G

• Contents: Evaluation Platform, DVI Adapter and CompactFlash Card
• Silicon Manufacturer: Xilinx
• Features: JTAG Programming Interface, Platform Flash, External Clocking
• Kit Contents: Board, Cable, PSU, CD, Docs
• Silicon Family Name: Virtex-5
• Silicon Core Number: XC5VSX50TFFG1136
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: XC5VSX50TFFG1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
R
CPU JTAG Header Pinout
CPU JTAG Connection to FPGA
Figure 1-8
the CPU with debug tools such as Parallel Cable IV or third party tools.
The connections between the CPU JTAG header (J12) and the FPGA are shown in
Table
using normal FPGA routing resources. The JTAG debug resources are not hard-wired to
particular pins and are available for attachment in the FPGA fabric, making it possible to
route these signals to the preferred FPGA pins.
Table 1-22: CPU JTAG Connection to FPGA
CPU_TDO
FPGA_SC0_B (CPU_TDI)
CPU_TRST_N
CPU_TCK
CPU_TMS
PC4_HALT_B
(CPU_HALT_N)
1-22. These are attached to the PowerPC® 440 processor JTAG debug resources
Pin Name
shows J12, the 16-pin header that can be used to debug the software operating in
CPU_HALT_N
Figure 1-8: CPU JTAG Header (J12)
www.xilinx.com
CPU_TMS
GND
J12
FPGA Pin (U1)
15
16
AF21
V10
U10
W9
E7
E6
1
2
CPU_TRST_N
CPU_VSENSE
CPU_TCK
CPU_TDI
CPU_TDO
UG347_07_111505
Connector Pin (J12)
Detailed Description
11
1
3
4
7
9
41