IC CPLD 128 MACROCELL 160LQFP

CY37128P160-125AC

Manufacturer Part NumberCY37128P160-125AC
DescriptionIC CPLD 128 MACROCELL 160LQFP
ManufacturerCypress Semiconductor Corp
SeriesUltra37000™
CY37128P160-125AC datasheet
 


Specifications of CY37128P160-125AC

Programmable TypeIn-System Reprogrammable™ (ISR™) CMOSDelay Time Tpd(1) Max10.0ns
Voltage Supply - Internal4.75 V ~ 5.25 VNumber Of Macrocells128
Number Of I /o133Operating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case160-LQFP
Voltage5VMemory TypeCMOS
For Use WithCY3710 - ADAPTER SOCKET PTGLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Features-Number Of Logic Elements/cells-
Other names428-1290  
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Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
• High density
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
• Simple timing model
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
• 3.3V and 5V versions
[1]
• PCI-compatible
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
— Product term sharing among local macrocells
• Flexible clocking
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
• Consistent package/pinout offering across all densities
— Simplifies design migration
— Same pinout for 3.3V and 5.0V devices
• Packages
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
BGA, and Fine-Pitch BGA packages
— Lead (Pb)-free packages available
Note:
1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V
Cypress Semiconductor Corporation
Document #: 38-03007 Rev. *E
5V, 3.3V, ISR™ High-Performance CPLDs
General Description
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and
In-System Reprogrammable (ISR), which simplifies both
design and manufacturing flows, thereby reducing costs. The
ISR feature provides the ability to reconfigure the devices
without having design changes cause pinout or timing
changes. The Cypress ISR function is implemented through a
JTAG-compliant serial interface. Data is shifted in and out
through the TDI and TDO pins, respectively. Because of the
superior routability and simple timing model of the Ultra37000
devices, ISR allows users to change existing logic designs
while
simultaneously
maintaining system performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. V
capability of interfacing to either a 5V or 3.3V bus. By
connecting the V
on the outputs. If V
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all V
pins, reducing the device’s power consumption. These
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
, PCI V
= 2V.
CC
IH
3901 North First Street
San Jose
Ultra37000 CPLD Family
fixing
pinout
assignments
connections provide the
CCO
pins to 5V the user insures 5V TTL levels
CCO
is connected to 3.3V the output levels
CCO
,
CA 95134
408-943-2600
Revised March 7, 2004
and
CCO

CY37128P160-125AC Summary of contents

  • Page 1

    ... BGA, and Fine-Pitch BGA packages — Lead (Pb)-free packages available Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V Cypress Semiconductor Corporation Document #: 38-03007 Rev. *E 5V, 3.3V, ISR™ High-Performance CPLDs General Description The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance ...

  • Page 2

    Selection Guide 5.0V Selection Guide General Information Device Macrocells CY37032 32 CY37064 64 CY37128 128 CY37192 192 CY37256 256 CY37384 384 CY37512 512 Speed Bins Device 200 167 CY37032 X CY37064 X CY37128 X CY37192 CY37256 CY37384 CY37512 Device-Package Offering ...

  • Page 3

    Speed Bins Device 200 167 CY37032V CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Device-Package Offering and I/O Count Device CY37032V 37 37 CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM ...

  • Page 4

    FROM PIM PRODUCT TERM ARRAY TO PIM Figure 1. Logic Block with 50% Buried Macrocells Low-Power Option Each logic block can operate in high-speed mode for critical path performance low-power mode for power conser- ...

  • Page 5

    The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried ...

  • Page 6

    FROM CLOCK 1 POLARITY MUXES 2 3 C10 INPUT/CLOCK PIN D 0 FROM CLOCK 1 O POLARITY INPUT 2 CLOCK PINS Clocking Each I/O and buried macrocell has access to four synchronous clocks (CLK0, ...

  • Page 7

    COMBINATORIAL SIGNAL INPUT REGISTERED SIGNAL D,T,L O INPUT CLOCK Figure 5. Timing Model for CY37128 JTAG and PCI Standards PCI Compliance 5V operation of the Ultra37000 is fully ...

  • Page 8

    The third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream ...

  • Page 9

    Logic Block Diagrams CY37032/CY37032V 16 I/Os −I/O I CY37064/CY37064V 16 I/Os I/O -I I/Os I/O -I TDI JTAG Tap TCK TDO Controller TMS Document #: 38-03007 Rev. *E Clock/ Input Input 4 1 ...

  • Page 10

    Logic Block Diagrams (continued) CY37128/CY37128V 16 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I CY37192/CY37192V 10 I/Os I/O –I I/Os I/O –I/O ...

  • Page 11

    Logic Block Diagrams (continued) CY37256/CY37256V 12 I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I/O 60 ...

  • Page 12

    Logic Block Diagrams (continued) CY37384/CY37384V 12 I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I/O 60 ...

  • Page 13

    Logic Block Diagrams (continued) CY37512/CY37512V 12 I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I I/Os −I/O I/O 60 ...

  • Page 14

    Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V ...

  • Page 15

    Inductance Parameter Description Test Conditions L Maximum Pin V = 5.0V IN Inductance MHz Capacitance [5] Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C Dual-Function Pins DP Endurance Characteristics [5] Parameter ...

  • Page 16

    Inductance Parameter Description Test Conditions L Maximum Pin V = 3.3V IN Inductance MHz Capacitance [5] Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C Dual Functional Pins DP Endurance Characteristics [5] ...

  • Page 17

    Parameter t 1.5V ER(–) t 2.6V ER(+) t 1.5V EA(+) t V EA(–) Switching Characteristics Over the Operating Range Parameter Combinatorial Mode Parameters [13, 14, 15] t Input to Combinatorial Output PD [13, 14, 15] t Input to Output ...

  • Page 18

    Switching Characteristics Over the Operating Range (continued) Parameter Product Term Clocking Parameters [13, 14, 15] t Product Term Clock or Latch Enable (PTCLK) to Output COPT t Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) SPT ...

  • Page 19

    Switching Characteristics Over the Operating Range 200 MHz 167 MHz 154 MHz Parameter Combinatorial Mode Parameters [13, 14, 15 6.5 PD [13, 14, 15 12.5 PDL [13, 14, 15 13.5 PDLL [13, 14, 15] ...

  • Page 20

    Switching Characteristics Over the Operating Range (continued) 200 MHz 167 MHz 154 MHz Parameter [13, 14, 15 [13 [13, 14, 15 User Option Parameters ...

  • Page 21

    Switching Waveforms (continued) Registered Output with Product Term Clocking Input Going Through the Array INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Latched Output ...

  • Page 22

    Switching Waveforms (continued) Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Document #: 38-03007 Rev ...

  • Page 23

    Switching Waveforms (continued) Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Document #: 38-03007 Rev. *E ...

  • Page 24

    Power Consumption Typical 5.0V Power Consumption CY37032 The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37064 9 0 ...

  • Page 25

    Typical 5.0V Power Consumption (continued) CY37128 The typical pattern is a 16-bit up counter, per logic ...

  • Page 26

    Typical 5.0V Power Consumption (continued) CY37256 The typical pattern is a 16-bit up counter, per logic block, with outputs ...

  • Page 27

    Typical 5.0V Power Consumption (continued) CY37512 The typical pattern is a 16-bit up counter, per logic block, with ...

  • Page 28

    Typical 3.3V Power Consumption (continued) CY37064V The typical pattern is a 16-bit up counter, per logic block, with outputs ...

  • Page 29

    Typical 3.3V Power Consumption (continued) CY37192V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37256V 1 ...

  • Page 30

    Typical 3.3V Power Consumption (continued) CY37384V The typical pattern is ...

  • Page 31

    Pin Configurations I/O /TCK 5 I/O I/O CLK 2 JTAG GND CLK 0 I/O I/O I/O I/O I/O 5 CLK JTAG CLK I/O Document #: 38-03007 Rev. *E 44-pin TQFP (A44) Top View ...

  • Page 32

    Pin Configurations (continued Note: 20. For 3.3V versions (Ultra37000V CCO I I /TCK I I/O 11 I/O 16 ...

  • Page 33

    Pin Configurations (continued) 100 TCK 1 GND CLK / ...

  • Page 34

    Pin Configurations (continued) 100-ball Fine-Pitch BGA (BB100) for CY37064V I/O 24 100-ball ...

  • Page 35

    Pin Configurations (continued) GND I I/O /TCK GND I I I/O ...

  • Page 36

    Pin Configurations (continued) GND I I TCK GND ...

  • Page 37

    Pin Configurations (continued) GND I TCK 8 I I/O 29 GND 13 ...

  • Page 38

    Pin Configurations (continued GND I/O NC I/O I/O I I/O I/O I/O I/O I/O I I/O NC I/O ...

  • Page 39

    Pin Configurations (continued GND GND I/O I GND I/O I/O I I/O I I/O I/O I ...

  • Page 40

    Pin Configurations (continued GND GND I/O I/O I/O I/O I/O I GND NC I/O I/O I/O I/O I/O I ...

  • Page 41

    Pin Configurations (continued) A GND GND NC I/O I/O I GND GND GND NC I/O I GND GND GND I/O I I/O NC GND I/O I/O I/O 44 ...

  • Page 42

    Ordering Information Cypress Semiconductor ID Family Type 37 = Ultra37000 Family Macrocell Density Macrocells 256 = 256 Macrocells ...

  • Page 43

    Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 64 154 CY37064P44-154AC CY37064P44-154JC CY37064P84-154JC CY37064P100-154AC CY37064P44-154AI CY37064P44-154AXI CY37064P44-154JI CY37064P44-154JXI CY37064P84-154JI CY37064P100-154AI 5962-9951902QYA 125 CY37064P44-125AC CY37064P44-125AXC CY37064P44-125JC CY37064P44-125JXC CY37064P84-125JC CY37064P100-125AC CY37064P100-125AXC CY37064P44-125AI CY37064P44-125AXI CY37064P44-125JI CY37064P84-125JI CY37064P100-125AI CY37064P100-125AXI 5962-9951901QYA Document #: 38-03007 ...

  • Page 44

    ... Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 128 167 CY37128P84-167JC CY37128P84-167JXC CY37128P100-167AC CY37128P100-167AXC CY37128P160-167AC CY37128P160-167AXC 125 CY37128P84-125JC CY37128P84-125JXC CY37128P100-125AC CY37128P100-125AXC CY37128P160-125AC CY37128P160-125AXC CY37128P84-125JI CY37128P84-125JXI CY37128P100-125AI CY37128P100-125AXI CY37128P160-125AI CY37128P160-125AXI 5962-9952102QYA 100 CY37128P84-100JC CY37128P84-100JXC CY37128P100-100AC CY37128P100-100AXC CY37128P160-100AC CY37128P160-100AXC CY37128P84-100JI CY37128P100-100AI CY37128P100-100AXI ...

  • Page 45

    Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 256 154 CY37256P160-154AC CY37256P160-154AXC CY37256P208-154NC CY37256P256-154BGC 125 CY37256P160-125AC CY37256P160-125AXC CY37256P208-125NC CY37256P256-125BGC CY37256P160-125AI CY37256P160-125AXI CY37256P208-125NI CY37256P256-125BGI 5962-9952302QZC 83 CY37256P160-83AC CY37256P160-83AXC CY37256P208-83NC CY37256P256-83BGC CY37256P160-83AI CY37256P160-83AXI CY37256P208-83NI CY37256P256-83BGI 5962-9952301QZC 384 125 CY37384P208-125NC CY37384P256-125BGC 83 ...

  • Page 46

    Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 512 125 CY37512P208-125NC CY37512P256-125BGC CY37512P352-125BGC 100 CY37512P208-100NC CY37512P256-100BGC CY37512P352-100BGC CY37512P208-100NI CY37512P256-100BGI CY37512P352-100BGI 5962-9952502QZC 83 CY37512P208-83NC CY37512P256-83BGC CY37512P352-83BGC CY37512P208-83NI CY37512P256-83BGI CY37512P352-83BGI 5962-9952501QZC 3.3V Ordering Information Speed Macrocells (MHz) Ordering Code 32 143 ...

  • Page 47

    Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 64 143 CY37064VP44-143AC CY37064VP44-143AXC CY37064VP48-143BAC CY37064VP100-143AC CY37064VP100-143AXC CY37064VP100-143BBC 100 CY37064VP44-100AC CY37064VP44-100AXC CY37064VP48-100BAC CY37064VP100-100AC CY37064VP100-100AXC CY37064VP100-100BBC CY37064VP44-100AI CY37064VP44-100AXI CY37064VP48-100BAI CY37064VP100-100BBI CY37064VP100-100AI CY37064VP100-100AXI 5962-9952001QYA 128 125 CY37128VP100-125AC CY37128VP100-125AXC CY37128VP100-125BBC CY37128VP160-125AC CY37128VP160-125AXC CY37128VP160-125AI CY37128VP160-125AXI ...

  • Page 48

    Ordering Information (continued) Speed Macrocells (MHz) Ordering Code 256 100 CY37256VP160-100AC CY37256VP160-100AXC CY37256VP208-100NC CY37256VP256-100BGC CY37256VP256-100BBC CY37256VP160-100AI CY37256VP160-100AXI 66 CY37256VP160-66AC CY37256VP160-66AXC CY37256VP208-66NC CY37256VP256-66BGC CY37256VP256-66BBC CY37256VP160-66AI CY37256VP256-66BGI CY37256VP256-66BBI 5962-9952401QZC 384 83 CY37384VP208-83NC CY37384VP256-83BGC 66 CY37384VP208-66NC CY37384VP256-66BGC CY37384VP208-66NI CY37384VP256-66BGI 512 83 CY37512VP208-83NC ...

  • Page 49

    Package Diagrams 44-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack A44 44-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J67 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85064-*B 51-85003-*A Page ...

  • Page 50

    Package Diagrams (continued) Document #: 38-03007 Rev. *E 44-Lead Ceramic Leaded Chip Carrier Y67 Ultra37000 CPLD Family 51-80014-** Page ...

  • Page 51

    Package Diagrams (continued) 48-Ball (7 7 1.2 mm, 0.80 pitch) Thin BGA BA48D 84-Lead Lead (Pb)-Free Plastic Leaded Chip Carrier J83 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85109-*C 51-85006-*A Page ...

  • Page 52

    Package Diagrams (continued) Document #: 38-03007 Rev. *E 84-Lead Ceramic Leaded Chip Carrier Y84 Ultra37000 CPLD Family 51-80095-*A Page ...

  • Page 53

    Package Diagrams (continued) 100-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85048-*B Page ...

  • Page 54

    Package Diagrams (continued) 100-Ball Thin Ball Grid Array ( 1.4 mm) BB100 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85107-*B Page ...

  • Page 55

    Package Diagrams (continued) 160-Lead Lead (Pb)-Free Thin Plastic Quad Flat Pack ( 1.4 mm) (TQFP) A160 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85049-*B Page ...

  • Page 56

    Package Diagrams (continued) 160-Lead Ceramic Quad Flatpack (Cavity Up) U162 PIN 1 SEATING PLANE 2.03(.080) 2.79(.110) 0.050(.002) 0.500(.020) Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 25.35±0.10 (.998±.004) TYP. 0.650(.0256) TYP. 0.300(.012) TYP. 28.00 ±0.10 (1.102 ±.004) SQ. 31.20 ±0.25 ...

  • Page 57

    Package Diagrams (continued) Document #: 38-03007 Rev. *E 208-Lead Plastic Quad Flatpack N208 Ultra37000 CPLD Family 51-85069-*B Page ...

  • Page 58

    Package Diagrams (continued) 208-Lead Ceramic Quad Flatpack (Cavity Up) U208 PIN 1 3.43(.135) 3.94(.155) SEATING PLANE 0.050(.002) 0.500(.020) Document #: 38-03007 Rev. *E 0.50(.0197) TYP. 0.20(.008) TYP. 28.00 ±0.10 (1.102 ±.008) SQ. 31.22 ±0.25 (1.229 ±.010) SQ. SEE DETAIL A ...

  • Page 59

    Package Diagrams (continued) TOP VIEW PIN 1 CORNER SEATING PLANE ...

  • Page 60

    Package Diagrams (continued) 292-Ball Plastic Ball Grid Array PBGA ( 2.33 mm) BG292 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85097-*B Page ...

  • Page 61

    Package Diagrams (continued) 388-Ball Plastic Ball Grid Array PBGA ( 2.33 mm) BG388 Document #: 38-03007 Rev. *E Ultra37000 CPLD Family 51-85103-*C Page ...

  • Page 62

    ... Document #: 38-03007 Rev. *E © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

  • Page 63

    Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143B Range Ambient Temperature Commercial Document #: 38-03007 Rev. *E Ultra37000 CPLD Family [2] Junction Temperature 0°C to +70°C 0°C to +90°C AC 3.3V ± 0.16V Page ...

  • Page 64

    ... CY37064P44-200AXC, CY37064P44-200JXC, CY37064P100-200AXC, CY37064P44-154AXI, CY37064P44-154JXI, CY37064P44-125AXC, CY37064P44-125JXC, CY37064P100-125AXC, CY37064P44-125AXI, CY37064P100-125AXI, CY37128P84-167JXC, CY37128P100-167AXC, CY37128P160-167AXC, CY37128P84-125JXC, CY37128P100-125AXC, CY37128P160-125AXC, CY37128P84-125JXI, CY37128P100-125AXI, CY37128P160-125AXI, CY37128P84-100JXC, CY37128P100-100AXC, CY37128P160-100AXC, CY37128P100-100AXI, CY37192P160-154AXC, CY37192P160-125AXC, CY37192P160-125AXI, CY37192P160-83AXC, CY37192P160-83AXI, CY37256P160-154AXC, CY37256P160-125AXC, CY37256P160-125AXI, CY37256P160-83AXC, CY37256P160-83AXI, CY37032VP44-143AXC, CY37032VP44-100AXC, CY37032VP44-100AXI, CY37032VP44-100JXI, CY37064VP44-143AXC, CY37064VP100-143AXC, CY37064VP44-100AXC, CY37064VP100-100AXC, CY37064VP44-100AXI, ...