ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 34

• Manufacturer Part Number: ADSP-21371KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21371KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21371
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-21368 SHARC Processor Hardware
Table 32. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
Source pins of DATA are DATA31–12 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SPCLKEN
HPCLKEN
PDSD
PDHD
PDCLKW
PDCLK
PDHLDD
PDSTRB
1
1
32. PDAP is the parallel mode operation of Channel 0 of
1
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
(PDAP_STROBE)
(PDAP_CLKEN)
DAI_P20
DAI_P20
(PDAP_CLK)
DAI_P20
DATA
-
-
1
-
1
1
Rev. 0 | Page 34 of 48 | June 2007
Figure 22. PDAP Timing
t
PDCLKW
SAMPLE EDGE
t
SPCLKEN
t
PDSD
t
PDHLDD
Reference. Note that the most significant 16 bits of external
PDAP data can be provided through the DATA31–16 pins. The
remaining four bits can only be sourced through DAI_P4–1.
The timing below is valid at the DATA31–16 pins.
t
PDCLK
t
HPCLKEN
t
PDHD
t
PDSTRB
Min
2.5
2.5
3.85
2.5
7
24
2 × t
2 × t
PCLK
PCLK
+ 3
– 1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns