ADSP-21261SKSTZ150 Analog Devices Inc, ADSP-21261SKSTZ150 Datasheet
ADSP-21261SKSTZ150
Specifications of ADSP-21261SKSTZ150
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ADSP-21261SKSTZ150 Summary of contents
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... I channels of audio when all four serial ports (SPORTs) are enabled or six full duplex TDM streams 128 channels per frame At 150 MHz (6.67 ns) core instruction rate, the ADSP-21261 operates at 900 MFLOPS peak/600 MFLOPS sustained per- ® port, four serial ...
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... DMA controller supports: 18 zero-overhead DMA channels for transfers between the ADSP-21261 internal memory and serial ports (eight), the input data port (IDP) (eight), the SPI-compatible port (one), and the parallel port (one) 32-bit background DMA transfers at core clock speed, in ...
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... Single-Cycle Fetch of Instruction and Four Operands ............................................... 5 Instruction Cache .............................................. 5 Data Address Generators with Zero-Overhead Hardware Circular Buffer Support ...................... 5 Flexible Instruction Set ....................................... 6 ADSP-21261 Memory and I/O Interface Features ......... 6 Dual-Ported On-Chip Memory ............................. 6 DMA Controller ................................................ 6 Digital Applications Interface (DAI) ....................... 6 Serial Ports ....................................................... 6 Serial Peripheral (Compatible) Interface .................. 7 Parallel Port ...
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... ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface. As shown in the Functional Block Diagram on Page 1, the ADSP-21261 uses two computational units to deliver a five to 10 times performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21261 DSP achieves an instruction cycle time of 6 ...
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... Circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21261 contain sufficient registers to allow the creation circular buff- ers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation ...
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... I/O processor sin- gle cycle. The ADSP-21261’s SRAM can be configured as a maximum of 48K words of 32-bit data, 46K words of 16-bit data, 31.5K words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to one megabit ...
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... FFFF). RESERVED 0x0300 0000–0x3FFF FFFF Figure 3. ADSP-21261 Memory Map 37.5 MHz, clock phases, and polarities. The ADSP-21261 SPI- compatible port uses open-drain drivers to support a multimas- ter configuration and to avoid data contention. Parallel Port The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15– ...
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... Timers The ADSP-21261 has a total of four timers: a core timer able to generate periodic software interrupts, and three general- purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
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... Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hard- ware tools include SHARC processor PC plug-in cards. Third- party software tools include DSP libraries, real-time operating systems, and block diagram design tools. Rev Page March 2006 ADSP-21261 ...
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... EZ-KIT Lite is a registered trademark of Analog Devices, Inc. ADDITIONAL INFORMATION ®† evaluation plat- This data sheet provides a general overview of the ADSP-21261 architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference ...
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... P = power supply synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state. Function Parallel Port Address/Data. The ADSP-21261 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ ...
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... ADSP-21261 SPI interaction, any of the master ADSP-21261’s flag pins can be used to drive the SPIDS signal on the ADSP-21261 SPI slave device. SPI Master Out Slave In. If the ADSP-21261 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21261 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
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... Three-state is a three-state driver, with pull-up disabled. Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21261 clock input. It configures the ADSP-21261 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator ...
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... ADSP-21261 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. Table 3. AD15–0 to FLAG Pin Mapping AD Pin Flag Pin AD0 FLAG8 AD1 FLAG9 AD2 FLAG10 AD3 FLAG11 AD4 FLAG12 ...
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... ADSP-21261 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage IH_CLKIN V Low Level Input Voltage @ V IL_CLKIN ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21261 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... TIMING SPECIFICATIONS The ADSP-21261’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’s internal clock frequency and exter- nal (CLKIN) clock frequency with the CLKCFG1– ...
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... ADSP-21261 Power-Up Sequencing The timing requirements for DSP startup are given in and Figure 6. Table 9. Power-Up Sequencing (DSP Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST t PLL Control Setup Before RESET Deasserted ...
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... CKH Figure 7. Clock Input Clock Signals The ADSP-21261 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21261 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- damental mode ...
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... ADSP-21261 Reset See Table 11 and Figure 9. Table 11. Reset Parameter Timing Requirements t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming 1 stable VDD and CLKIN (not including start-up time of external clock oscillator) ...
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... PWI DAI_P20–1 (TIMER) Figure 12 applies to Min 2 t – 1 CCLK t PWMO Figure 12. Timer PWM_OUT Timing Figure 13 applies to Min 2 t CCLK t PWI Figure 13. Timer Width Capture Timing Rev Page March 2006 ADSP-21261 Max Unit 31 2(2 – CCLK Max Unit 31 2(2 – CCLK ...
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... ADSP-21261 DAI Pin-to-Pin Direct Routing See Table 16 and Figure 14 for direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 16. DAI Pin-to-Pin Direct Routing Parameter Timing Requirement t Delay DAI Pin Input Valid to DAI Output Valid DPIO DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin-to-Pin Direct Routing Rev ...
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... All timing parameters and switching characteris- tics apply to external DAI pins (DAI_P07 – DAI_P20). t STRIG t HTRIG t DPCGIO t DTRIG Figure 15. Precision Clock Generator (Direct Pin Routing) Rev Page March 2006 ADSP-21261 Min Max 2.5 10 2.5 + 2.5 × 2.5 × t PCGOW PCGOW ...
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... ADSP-21261 Flags The timing specifications in Table 18 and FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 2 on Page 11 tion on flag use. Table 18. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width FIPW Switching Characteristic t FLAG3–0 OUT Pulse Width FOPW DAI_P20– ...
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... Memory Read—Parallel Port The specifications in Table 19, Table 20, Figure 18 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is access- ing external memory space. Table 19. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data7–0 Setup Before RD High DRS t Address/Data7–0 Hold After RD High ...
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... ADSP-21261 Table 20. 16-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data15–0 Setup Before RD high DRS t Address/Data15–0 Hold After RD high DRH Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data15–0 Setup Before ALE Deasserted ADAS t Address/Data15–0 Hold After ALE Deaserted ...
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... Memory Write—Parallel Port Use the specifications in Table 21, Table Figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21261 is access- ing external memory space. Table 21. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ...
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... ADSP-21261 Table 22. 16-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data 15–0 Setup Before ALE Deasserted ADAS t Address/Data15–0 Hold After ALE Deasserted ADAH t WR Pulse Width ALE Deasserted to Address/Data15–0 in High Z ALEH t Address/Data15– ...
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... Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 23, Table 24, must be confirmed Rev Page March 2006 ADSP-21261 Min Max Unit 2.5 ns 2.5 ns 2 Min Max Unit ...
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... ADSP-21261 Table 25. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 26. Serial Ports—External Late Frame Sync ...
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... DAI_P20–1 (SCLK HFSI SFSI DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) t DDTEN t DDTIN Figure 22. Serial Ports Rev Page March 2006 ADSP-21261 DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE ...
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... ADSP-21261 Input Data Port (IDP) The timing requirements for the IDP are given in Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 27. Input Data Port (IDP) ...
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... The timing requirements for the PDAP are provided in and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 28. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements t ...
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... ADSP-21261 SPI Protocol—Master Table 29. SPI Protocol—Master Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Setup Time) SSPIDM t SPICLK Last Sampling Edge to Data Input Not Valid HSPIDM Switching Characteristics t Serial Clock Cycle SPICLKM t Serial Clock High Period SPICHM ...
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... MISO MSB (OUTPUT) CPHASE = 0 MOSI MSB VALID (INPUT MSB LSB VALID LSB LSB VALID Figure 26. SPI Protocol—Slave Rev Page March 2006 ADSP-21261 Min Max Unit 4 × CCLK 2 × t – CCLK 2 × t – CCLK 2 × CCLK 2 × CCLK 2 × CCLK × t ...
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... ADSP-21261 JTAG Test Access Port and Emulation See Table 31 and Figure 27. Table 31. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output driv- ers of the ADSP-21261. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 70°C 0 –10 3.3V, 25°C 3.11V, 70°C –20 – 3.47V, 0°C – ...
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... LOAD CAPACITANCE (pF) Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-21261 processor is rated for performance over the commercial temperature range 0°C to 70°C. AMB THERMAL CHARACTERISTICS Table 32 and Table 33 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... BGA PIN CONFIGURATIONS Table 34 shows the ADSP-21261’s pin names and their default function after reset (in parentheses). Figure 34 on Page 41 shows the BGA package pin assignments. Table 34. 136-Ball BGA Pin Assignments Pin Name Ball No. Pin Name CLKCFG0 A01 CLKCFG1 XTAL ...
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... ADSP-21261 Table 34. 136-Ball BGA Pin Assignments (Continued) Pin Name Ball No. Pin Name AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) ...
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... KEY V A GND DDINT VDD V A I/O SIGNALS DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev Page March 2006 ADSP-21261 ...
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... ADSP-21261 144-LEAD LQFP PIN CONFIGURATIONS Table 35 shows the ADSP-21261’s pin names and their default function after reset (in parentheses). Table 35. 144-Lead LQFP Pin Assignments LQFP Pin Name Pin No. Pin Name DDINT DDINT CLKCFG0 2 GND CLKCFG1 3 RD BOOTCFG0 4 ALE BOOTCFG1 5 AD15 GND ...
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... PACKAGE DIMENSIONS The ADSP-21261 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. ...
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... Model Range ADSP-21261SKBC-150 0°C to +70°C 2 ADSP-21261SKBCZ150 0°C to +70°C 2 ADSP-21261SKSTZ150 0°C to +70°C 1 Ranges shown represent ambient temperature Pb-free part. © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Ball Pad Size 0 ...