ADSP-21261SKSTZ150 Analog Devices Inc, ADSP-21261SKSTZ150 Datasheet - Page 23

• Manufacturer Part Number: ADSP-21261SKSTZ150
• Description: IC DSP 32BIT 150MHZ 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKSTZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 150MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic: RoHS Compliant
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 150 MHz
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Precision Clock Generator (Direct Pin Routing)
The timing in
SRU is configured such that the precision clock generator
(PCG) takes its inputs directly from the DAI pins (via pin buff-
ers) and sends its outputs directly to the DAI pins. For the other
Table 17. Precision Clock Generator (Direct Pin Routing)
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
PCGIW
STRIG
HTRIG
DPCGIO
DTRIG
PCGOW
Table 17
Input Clock Pulse Width
PCG Trigger Setup Before Falling Edge of PCG Input Clock
PCG Trigger Hold After Falling Edge of PCG Input Clock
PCG Output Clock and Frame Sync Active Edge Delay After PCG Input
Clock Falling Edge
PCG Output Clock and Frame Sync Delay After PCG Trigger
Output Clock Pulse Width
PCG_CLKx_O
PCG_TRIGx_I
and
PCG_EXTx_I
PCG_FSx_O
Figure 15
DAI_Pm
(CLKIN)
DAI_Pn
DAI_Py
DAI_Pz
is valid only when the
Figure 15. Precision Clock Generator (Direct Pin Routing)
t
STRIG
Rev. 0 | Page 23 of 44 | March 2006
t
HTRIG
t
DTRIG
t
DPCGIO
cases where the PCG’s inputs and outputs are not directly
routed to/from DAI pins (via pin buffers) there is no timing
data available. All timing parameters and switching characteris-
tics apply to external DAI pins (DAI_P07 – DAI_P20).
t
PCGIW
Min
20
2
2
2.5
2.5 + 2.5 × t
40
t
PCGOW
PCGOW
Max
10
10 + 2.5 × t
ADSP-21261
PCGOW
Unit
ns
ns
ns
ns
ns
ns