0W344-005-XTP ON Semiconductor, 0W344-005-XTP Datasheet - Page 18

• Manufacturer Part Number: 0W344-005-XTP
• Description: DSP BELASIGNA 200 AUDIO 52-NQFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 200r
• Type: Fixed Pointr

Specifications of 0W344-005-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 33MHz
• On-chip Ram: 42kB
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-TFQFN
• Device Core Size: 16b
• Architecture: Dual Harvard
• Format: Fixed Point
• Ram Size: 16KB
• Program Memory Size: 24KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -
• Voltage - I/o: -
• Voltage - Core: -
• Lead Free Status / Rohs Status: Compliant

BelaSigna 200
7.0 Instruction Set
Table 6: Instruction Set
Instruction
ABS A [,Cond] [,DW]
ADD A, Reg [,C]
ADD A, (Rij) [,C]
ADD A, DRAM [,B]
ADD A, (Rij)p [,C]
ADD A, Rc [,C]
ADDI A, IMM [,C]
ADSI A, SIMM
AND A, Reg
AND A, (Rij)
AND A, DRAM [,B]
AND A, (Rij)p
AND A, Rc
ANDI A, IMM
ANSI A, SIMM
BRA PRAM [,Cond]
BREAK
CALL PRAM [,Cond] [,B]
CLB A
CLR A [,DW]
CLR Reg
CMP A, Reg [,C]
CMP A, (Rij) [,C]
CMP A, DRAM [,B]
CMP A, (Rij)p [,C]
CMP A, Rc [,C]
CMPI A, IMM [,C]
CMSI A, SIMM
CMPL A [,Cond] [,DW]
DADD [Cond] [,P]
DBNZ0/1 PRAM
Description
Calculate absolute value of A on condition
Add register to A
Add memory to A
Add (DRAM) to A
Add program memory to A
Add Rc register to A
Add IMM to A
Add signed SIMM to A
AND register with AH to AH
AND memory with AH to AH
AND (DRAM) with AH to AH
AND program memory with AH to AH
AND Rc register with AH to AH
AND IMM with AH to AH
AND unsigned SIMM with AH to AH
Branch to new address on condition
Stop the DSP for debugging purposes
Push PC and branch to new address
on condition
Calculate the leading bits on A
Clear accumulator
Clear register
Compare register to A
Compare memory to A
Compare (DRAM) to A
Compare program memory to A
Compare Rc register to A
Compare IMM to A
Compare signed SIMM to A
Calculate logical inverse of A on condition
Add PH | PL to A, update PH | PL
on condition
Branch to new address if LC0/1 <> 0
Rev. 16 | Page 18 of 43 | www.onsemi.com
Instruction
DCMP
DEC A [,Cond] [,DW]
DEC Reg [Cond]
DEC (Rij) [,Cond]
DSUB [Cond] [,P]
EOR A, Reg
EOR A, (Rij)
EOR A, DRAM [,B]
EOR A, (Rij)p
EOR A, Rc
EORI A, IMM
EOSI A, SIMM
INC A [,Cond] [,DW]
INC Reg [,Cond]
INC (Rij) [,Cond]
LD Rc, Rc
LD Reg, Reg
LD Reg, (Rij)
LD (Rij), Reg
LD A, DRAM [,B]
LD DRAM, A [,B]
LD Rc, (Rij)
LD (Rij), Rc
LD Reg, (Rij)p
LD (Rij)p, Reg
LD Reg, (Reg)p
LD Reg, Rc
LD Rc, Reg
LDI Reg, IMM
LDI Rc, IMM
LDI (Rij), IMM
Description
Compare PH | PL to A
Decrement A on condition
Decrement register on condition
Decrement memory on condition
Subtract PH | PL from A,
update PH | PL on condition
Exclusive-OR register with AH to AH
Exclusive-OR memory with AH to AH
Exclusive-OR (DRAM) with AH to AH
Exclusive-OR program memory with
AH to AH
Exclusive-OR Rc register with AH to
AH
Exclusive-OR IMM with AH to AH
Exclusive-OR unsigned SIMM with AH
to AH
Increment A on condition
Increment register on condition
Increment memory on condition
Load Rc register with Rc register
Load register with register
Load register with memory
Load memory with register
Load A with (DRAM)
Load (DRAM) with A
Load Rc register with memory
Load memory with Rc register
Load register with program memory
Load program memory with register
Load register with program memory via
register
Load register with Rc register
Load Rc register with register
Load register with IMM
Load Rc register with IMM
Load memory with IMM