AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet
AD14060BF-4
Specifications of AD14060BF-4
Related parts for AD14060BF-4
AD14060BF-4 Summary of contents
Page 1
PERFORMANCE FEATURES ADSP-21060 core processor ( × 4) 480 MFLOPS peak, 320 MFLOPS sustained 25 ns instruction rate, single-cycle instruction execution—each of four processors 16 Mbit shared SRAM (internal to SHARCs) 4 gigawords addressable off-module memory Twelve 40 Mbyte/s link ...
Page 2
AD14060/AD14060L TABLE OF CONTENTS Specifications..................................................................................... 3 Electrical Characteristics (3 Supply)............................ 3 Explanation of Test Levels........................................................... 4 Timing Specifications....................................................................... 5 Memory Read—Bus Master........................................................ 8 Memory Write—Bus Master ....................................................... 9 Synchronous Read/Write—Bus Master................................... 10 Synchronous Read/Write—Bus Slave ...................................... 12 ...
Page 3
SPECIFICATIONS Table 1. Recommended Operating Conditions Parameter V Supply Voltage ( Supply Voltage (3 Case Operating Temperature CASE ELECTRICAL CHARACTERISTICS (3 SUPPLY) Table 2. Parameter 1 V High Level Input Voltage IH1 2 ...
Page 4
AD14060/AD14060L EXPLANATION OF TEST LEVELS Test Level I 100% production tested 100% production tested at 25°C, and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and analysis, and characterization testing on ...
Page 5
TIMING SPECIFICATIONS This data sheet represents production-released specifications for the AD14060 (5 V), and for the AD14060L (3.3 V). The ADSP-21060 die components are 100% tested, and the assembled AD14060/AD14060L units are again extensively tested at speed and across temperature. ...
Page 6
AD14060/AD14060L Table 4. Reset Parameter Reset Timing Requirements RESET Pulse Width Low WRST t RESET Setup before CLKIN High SRST 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more ...
Page 7
Table 6. Timer Parameter Timer Switching Characteristic: t CLKIN High to TIMEXP DTEX CLKIN t DTEX TIMEXP Table 7. Flags Parameter Flags Timing Requirements: t FLAG2-0 Setup before CLKIN High SFI IN t FLAG2-0 Hold after CLKIN High HFI IN ...
Page 8
AD14060/AD14060L MEMORY READ—BUS MASTER Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space. These switching characteristics also apply for bus ...
Page 9
MEMORY WRITE—BUS MASTER Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space. These switching characteristics also apply for bus master ...
Page 10
AD14060/AD14060L SYNCHRONOUS READ/WRITE—BUS MASTER Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory reads and ...
Page 11
CLKIN t DADCCK ADRCLK t DADRO ADDRESS SW t DPGC PAGE ACK (IN) READ CYCLE t DRWL RD DATA (IN) WRITE CYCLE t DRWL WR DATA (OUT) t ADRCK t ADRCKH t DAAK t SACKC t SDDATO Figure 9. Synchronous ...
Page 12
AD14060/AD14060L SYNCHRONOUS READ/WRITE—BUS SLAVE Use these specifications for bus master access to a slave’s IOP registers or internal memory in multiprocessor memory space. The bus master must meet these bus slave timing requirements. Table 11. Specifications Parameter Timing Requirements: t ...
Page 13
MULTIPROCESSOR BUS REQUEST AND HOST BUS REQUEST Use these specifications for passing of the bus mastership among multiprocessing ADSP-2106xs ( host processor ( HBR , HBG ). Table 12. Specifications Parameter Timing Requirements HBG ...
Page 14
AD14060/AD14060L CLKIN t SHBRI HBR HBG (OUT) BRx (OUT) CPA (OUT) (O/D) HBG (IN) BRx (IN) CPA (IN) (O/D) HBR CS t DRDYCS REDY (O/D) REDY (A/D) HBG (OUT SRPBAI RPBA O/D = OPEN DRAIN, A/D ...
Page 15
ASYNCHRONOUS READ/WRITE—HOST TO AD14060/AD14060L Use these specifications for asynchronous host processor access to an AD14060/AD14060L, after the host has asserted CS and HBR (low). After HBG is returned by the AD14060/AD14060L, the host can drive the RD and WR pins ...
Page 16
AD14060/AD14060L READ CYCLE ADDRESS/CS RD DATA (OUT) REDY (O/D) REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE t SADRDL t SDATRDY t t DRDYRDL RDYPRD t SCSWRL ...
Page 17
THREE-STATE TIMING—BUS MASTER, BUS SLAVE, HBR, SBTS These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and ...
Page 18
AD14060/AD14060L DMA HANDSHAKE These specifications describe the three DMA handshake modes. In all three modes, DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer ...
Page 19
CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (FROM ADSP-2106x TO EXTERNAL DRIVE) DATA (FROM EXTERNAL DRIVE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL ...
Page 20
AD14060/AD14060L Table 16. 1× CLK Speed Operation Parameter Receive Timing Requirements: t Data Setup before LCLK Low SLDCL t Data Hold after LCLK Low HLDCL t LCLK Period (1× Operation) LCLKIW t LCLK Width Low LCLKRWL t LCLK Width High ...
Page 21
Table 17. 2× CLK Speed Operation Parameter Receive Timing Requirements: t Data Setup before LCLK Low SLDCL t Data Hold after LCLK Low HLDCL t LCLK Period (2× Operation) LCLKIW t LCLK Width Low LCLKRWL t LCLK Width High LCLKRWH ...
Page 22
AD14060/AD14060L TRANSMIT CLKIN t DLCLK t t LCLKTWH LCLKTWL LCLK 1x OR LCLK 2x t DLDCH t HLDCH LDAT(3:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH RECEIVE ...
Page 23
Table 18. Serial Ports Parameter External Clock Timing Requirements: t TFS/RFS Setup before TCLK/RCLK SFSE t TFS/RFS Hold after TCLK/RCLK HFSE t Receive Data Setup before RCLK SDRE t Receive Data Hold after RCLK HDRE t TCLK/RCLK Width SCLKW t ...
Page 24
AD14060/AD14060L Parameter External Late Frame Sync Switching Characteristics: t Data Delay from Late External TFS or External RFS DDTLFSE 4 with MCE = 1, MFD = 0 t Data Enable from Late FS or MCE = 1, MFD = 0 ...
Page 25
DATA RECEIVE– INTERNAL CLOCK DRIVE SAMPLE EDGE EDGE t SCLKIW RCLK t DFSE t t HFSE SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. ...
Page 26
AD14060/AD14060L Table 19. JTAG Test Access Port and Emulation Parameter Timing Requirements: t TCK Period TCK t TDI, TMS Setup before TCK High STAP t TDI, TMS Hold after TCK High HTAP t System Inputs Setup before TCK Low SSYS ...
Page 27
ABSOLUTE MAXIMUM RATINGS Table 20. Parameters Supply Voltage (5 V) Supply Voltage (3.3 V) Input Voltage Output Voltage Swing Load Capacitance Junction Temperature under Bias Storage Temperature Range Lead ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high ...
Page 28
AD14060/AD14060L PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 308 1 AD14060/AD14060L TOP VIEW 77 78 Figure 20. 308-Lead CQFP Pin Configuration Rev Page 232 231 155 154 ...
Page 29
Table 21. Pin Numbers and Mnemonics Pin Pin No. Mnemonic No. Mnemonic GND RFSD1 3 GND 47 RCLKD1 4 CSA 48 DRD1 5 CSB 49 TFSD1 6 CSC 50 TCLKD1 7 CSD 51 DTD1 ...
Page 30
AD14060/AD14060L PIN FUNCTION DESCRIPTIONS AD14060/AD14060L pin function descriptions are listed in Table 22. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can ...
Page 31
Pin Type Function SBTS I/S Suspend Bus Three-State (common to all SHARCs). External devices can assert SBTS (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. If the ...
Page 32
AD14060/AD14060L 1 Pin Type Function FLAG1 I/O/A Flag Pins (FLAG1 common to all SHARCs). This pin is configured via control bits internal to individual ADSP-21060s as either an input or an output input, it can be tested as ...
Page 33
Pin Type Function TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A. TDI has a 20 kΩ internal pull-up resistor. TDO O Test Data Output (JTAG). Serial scan output of ...
Page 34
AD14060/AD14060L DETAILED DESCRIPTION ARCHITECTURAL FEATURES ADSP-21060 Core The AD14060/AD14060L is based on the powerful ADSP-21060 (SHARC) DSP chip. The ADSP-21060 SHARC combines a high performance floating-point DSP core with integrated, on-chip system features, including a 4-Mbit SRAM memory, host processor ...
Page 35
CORE PROCESSOR INSTRUCTION TIMER CACHE 32 x 48-BIT DAG1 DAG2 PROGRAM SEQUENCER PM ADDRESS BUS 24 DM ADDRESS BUS 32 PM DATA BUS 48 BUS CONNECT 40/32 DM DATA BUS ...
Page 36
AD14060/AD14060L INTERNAL MEMORY SPACE (INDIVIDUAL SHARCs) INTERNAL TO AD14060 MULTIPROCESSOR MEMORY SPACE EXTERNAL TO AD14060 NORMAL WORD ADDRESSING: 32-BIT DATA WORDS SHORT WORD ADDRESSING: 16-BIT DATA WORDS Bus locking is possible, allowing indivisible read-modify-write sequences for semaphores. In either the ...
Page 37
AD14060/ AD14060L 1x CLKIN CLOCK RESET RESET RPBA CONTROL SERIALS LINKS DISCRETES ADSP-2106x #5 (OPTIONAL) CLKIN RESET RPBA 3 101 ID 2–0 CONTROL ADSP-2106x #6 (OPTIONAL) CLKIN RESET RPBA 3 110 ID 2–0 CONTROL Figure 24. Optional System Interconnections Rev. ...
Page 38
AD14060/AD14060L LINK PORT I/O Each individual SHARC features six 4-bit link ports that facilitate SHARC-to-SHARC communication and external I/O interfacing. Each link port can be configured for either 1× or 2× operation, allowing each to transfer either four or eight ...
Page 39
Multiprocessor EPROM Booting The following methods boot the multiprocessor system from an EPROM: • SHARC_A is booted, which then boots the others. The EBOOT pin on the SHARC_A must be set high for EPROM booting. All other ADSP-21060s should be ...
Page 40
AD14060/AD14060L APPLICATIONS DEVELOPMENT TOOLS The AD14060/AD14060L is supported with a complete set of software and hardware development tools, including an in-circuit emulator and development software. Analog Devices, Inc. (ADI) uses VisualDSP++®, which is an easy-to-use integrated software development and debugging ...
Page 41
GND EMU 3 4 KEY (NO PIN) CLKIN (OPTIONAL BTMS TMS 7 8 BTCK TCK 9 10 BTRST 9 TRST 11 12 BTDI TDI 13 14 GND TDO TOP VIEW Figure 26. Target Board Connector for ...
Page 42
AD14060/AD14060L SHARC_A TDI TDI TDO EMULATOR JTAG CONNECTOR OTHER JTAG TCK CONTROLLER TMS EMU TRST TDO CLKIN OPTIONAL TDI EMU TCK TMS TRST TDO CLKIN OUTPUT DRIVE CURRENTS Figure 29 shows typical I-V characteristics for the output drivers of the ...
Page 43
The load capacitance should include the processor’s package capacitance (C ). The switching frequency includes driving the IN load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/(2 t ...
Page 44
AD14060/AD14060L Capacitive Loading Output delays and holds are based on standard capacitive loads all pins (see Figure 31). The delay and hold specifica- tions given should be derated by a factor of 1.5 ns/50 pF for loads ...
Page 45
Y = 0.0391X + 0. RISE TIME 3 FALL TIME 100 120 LOAD CAPACITANCE (pF) Figure 37. Typical Output Rise Time (0 2.0 V) ...
Page 46
AD14060/AD14060L PCB LAYOUT GUIDELINES The drawing in Figure 40 assumes that the trim/form tooling described previously is used. These recommendations are provided for user convenience and are PCB layout guidelines only, based on standard practice. PCB pad footprint geometries and ...
Page 47
MECHANICAL CHARACTERISTICS Lid Deflection Analysis Table 28. External Pressure Reduction Δ Pressure Deflection 12 psi 10.0 mil 15 psi 11.9 mil Mechanical Model The following data, together with the detailed mechanical drawings in Figure 43, allows the designer to construct ...
Page 48
... MAX 0.092 (2.337) 0.083 (2.108) ORDERING GUIDE Temperature Model Range AD14060BF-4 −40°C to +100°C AD14060LBF-4 −40°C to +100°C © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 3.050 (77.47) MAX 3 ...