AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 17

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

THREE-STATE TIMING—BUS MASTER, BUS SLAVE, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the
SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Table 14. Specifications
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
ADCEN
ADCTR
MTRHBG
MENHBG
Strobes = RD , WR , SW , PAGE, DMAG .
In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.
Memory interface = address, RD , WR , MS x, SW , HBG , PAGE, DMAG x, BMS (in EPROM boot mode).
INTERFACE
INTERFACE
MEMORY
MEMORY
ADRCLK
SBTS Setup before CLKIN
SBTS Hold before CLKIN
Address/Select Enable after CLKIN
Strobes Enable after CLKIN
HBG Enable after CLKIN
Address/Select Disable after CLKIN
Strobes Disable after CLKIN
HBG Disable after CLKIN
Data Enable after CLKIN
Data Disable after CLKIN
ACK Enable after CLKIN
ACK Disable after CLKIN
ADRCLK Enable after CLKIN
ADRCLK Disable after CLKIN
Memory Interface Disable before HBG Low
Memory Interface Enable after HBG High
CLKIN
SBTS
DATA
ACK
HBG
MEMORY INTERFACE
t
ADCEN
t
ACKEN
t
t
MIENA
DATEN
2
2
2
2
,
t
= ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
MIENS
1
1
,
t
t
MIENHG
MENHBG
t
STSCK
3
3
Figure 14. Three-State Timing
t
HTSCK
Rev. B | Page 17 of 48
−2 − DT/8
Min
12.5 + DT/2
−1.5 − DT/8
−1.5 − DT/8
−1.5 − DT/8
9 + 5 DT/16
0 − DT/8
7.5 + DT/4
−1 − DT/8
−1 + DT/8
18.5 + DT
t
ADCTR
t
t
DATTR
ACKTR
t
MITRA
5 V
,
t
MITRS
Max
5.5 + DT/2
1 − DT/4
2.5 − DT/4
3 − DT/4
8 − DT/8
+7 − DT/8
9 − DT/4
,
t
MITRHG
Min
12.5 + DT/2
−1.25 − DT/8
−1.5 − DT/8
−1.5 − DT/8
9 + 5 DT/16
0 − DT/8
7.5 + DT/4
−1 − DT/8
−2 − DT/8
−1 + DT/8
18.5 + DT
t
MTRHBG
AD14060/AD14060L
3.3 V
Max
5.5 + DT/2
1.25 − DT/4
2.5 − DT/4
3 − DT/4
8 − DT/8
+7 − DT/8
9 − DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns