XC3S500E-4FGG320C Xilinx Inc, XC3S500E-4FGG320C Datasheet - Page 129

• Manufacturer Part Number: XC3S500E-4FGG320C
• Description: IC SPARTAN-3E FPGA 500K 320FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FGG320C

• Total Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Number Of I /o: 232
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 320-BGA
• No. Of Logic Blocks: 10476
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• No. Of Speed Grades: 4
• No. Of I/o's: 250
• Clock Management: DLL
• Package: 320FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1526

Table 88: Setup and Hold Times for the IOB Input Path
Table 89: Sample Window (Source Synchronous)
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Setup Times
T
T
Hold Times
T
T
Set/Reset Pulse Width
T
T
Symbol
Symbol
IOPICK
IOPICKD
IOICKP
IOICKPD
RPW_IOB
SAMP
The numbers in this table are tested using the methodology presented in
Table 77
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
R
Time from the setup of data at the
Input pin to the active transition at the
ICLK input of the Input Flip-Flop
(IFF). No Input Delay is
programmed.
Time from the setup of data at the
Input pin to the active transition at the
IFF’s ICLK input. The Input Delay is
programmed.
Time from the active transition at the
IFF’s ICLK input to the point where
data must be held at the Input pin. No
Input Delay is programmed.
Time from the active transition at the
IFF’s ICLK input to the point where
data must be held at the Input pin.
The Input Delay is programmed.
Minimum pulse width to SR control
input on IOB
and
Setup and hold capture window of
an IOB input flip-flop
Table
80.
Description
Description
Table
Table
91.
91. When the hold time is negative, it is possible to change the data before the clock’s active
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
LVCMOS25
IFD_DELAY_VALUE = 0
LVCMOS25
IFD_DELAY_VALUE =
default software setting
The input capture sample window value is highly specific to a
particular application, device, package, I/O standard, I/O
placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx application note for application-specific
values.
• XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at
Speeds Up to 666 Mbps
Conditions
www.xilinx.com
(2)
(2)
(2)
(2)
,
,
,
,
Table 95
VALUE=
DELAY_
IFD_
and are based on the operating conditions set forth in
0
2
3
0
2
3
Max
XC3S100E
XC3S100E
All Others
All Others
Device
DC and Switching Characteristics
All
All
All
–0.76
–3.93
–3.50
1.84
6.12
6.76
1.57
Min
Speed Grade
-5
–0.76
–3.93
–3.50
2.12
7.01
7.72
1.80
Min
-4
Units
Units
ps
ns
ns
ns
ns
ns
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