XC3S500E-4FGG320C Xilinx Inc, XC3S500E-4FGG320C Datasheet - Page 45

• Manufacturer Part Number: XC3S500E-4FGG320C
• Description: IC SPARTAN-3E FPGA 500K 320FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4FGG320C

• Total Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Number Of I /o: 232
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 320-BGA
• No. Of Logic Blocks: 10476
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• No. Of Speed Grades: 4
• No. Of I/o's: 250
• Clock Management: DLL
• Package: 320FBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1526

DS312-2 (v3.8) August 26, 2009
Product Specification
BCIN[17:0]
A[17:0]
B[17:0]
RSTB
RSTP
RSTA
CEA
CEB
CEP
CLK
Figure 37: MULT18X18SIO Primitive
R
MULT18X18SIO
B[17:0]
RSTB
RSTB
CEB
CEB
CLK
CLK
BCIN[17:0]
Figure 38: Four Configurations of the B Input
CE
D
CE
D
BREG
BREG
BCOUT[17:0]
RST
RST
BCOUT[17:0]
P[35:0]
BCOUT[17:0]
DS312-2_28_021205
Q
Q
BREG = 1
B_INPUT = CASCADE
BREG = 1
B_INPUT = DIRECT
www.xilinx.com
X
X
Cascading Multipliers
The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the multi-
plier’s ‘B’ input among several multiplier bocks. The 18-bit
BCIN “cascade” input port offers an alternate input source
from the more typical ‘B’ input. The B_INPUT attribute spec-
ifies whether the specific implementation uses the BCIN or
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
input. Setting B_INPUT to CASCADE selects the alternate
BCIN input. The BREG register then optionally holds the
selected input value, if required.
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
Figure 38
different settings for the B_INPUT attribute and the BREG
attribute.
B[17:0]
BCOUT[17:0]
BCOUT[17:0]
BCIN[17:0]
illustrates the four possible configurations using
BREG = 0
B_INPUT = CASCADE
BREG = 0
B_INPUT = DIRECT
DS312-2_29_021505
X
X
Functional Description
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