XA6SLX9-3CSG324I Xilinx Inc, XA6SLX9-3CSG324I Datasheet
XA6SLX9-3CSG324I
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XA6SLX9-3CSG324I Summary of contents
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DS162 (v2.0) March 31, 2011 Spartan-6 FPGA Electrical Characteristics Spartan®-6 LX FPGAs are available in -3, -3N, -2, and -1L speed grades, with -3 having the highest performance. Spartan-6 LXT FPGAs are available in -3, -3N, and -2 speed grades, ...
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Table 1: Absolute Maximum Ratings Symbol T Storage temperature (ambient) STG Maximum soldering temperature (TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256) T SOL Maximum soldering temperature Maximum soldering temperature T Maximum junction temperature j Notes: 1. Stresses beyond those listed ...
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Table 2: Recommended Operating Conditions Symbol Description Maximum current through pin using PCI I/O standard when forward biasing the (10) I clamp diode. IN Battery voltage relative to GND +85C (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) ...
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Table 4: DC Characteristics Over Recommended Operating Conditions Symbol V Data retention V voltage (below which configuration data might be lost) DRINT CCINT V Data retention V voltage (below which configuration data might be lost) DRAUX CCAUX I V leakage ...
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Quiescent Current Typical values for quiescent supply current are specified at nominal voltage, 25°C junction temperatures (T supply current is specified by speed grade for Spartan-6 devices. Xilinx recommends analyzing static power consumption using the XPOWER™ Estimator (XPE) tool (download ...
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Table 5: Typical Quiescent Supply Current (Cont’d) Symbol Description I Quiescent V supply current CCAUXQ CCAUX Notes: 1. Typical values are specified at nominal voltage, 25°C junction temperatures (T commercial (C) grade devices at 25°C, but higher values at 100°C. ...
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SelectIO™ Interface DC Input and Output Levels Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards I/O Standard V, Min LVTTL 3.0 LVCMOS33 3.0 LVCMOS25 2.3 LVCMOS18 1.65 LVCMOS18_JEDEC 1.65 LVCMOS15 1.4 LVCMOS15_JEDEC 1.4 LVCMOS12 1.1 LVCMOS12_JEDEC 1.1 ...
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Table 8: Recommended Operating Conditions for User I/Os Using Differential Signal Standards I/O Standard LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 (1) LVPECL_33 LVPECL_25 RSDS_33 RSDS_25 (1) TMDS_33 PPDS_33 PPDS_25 DISPLAY_PORT DIFF_MOBILE_DDR DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II ...
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In Table 9 and Table 10, values for V the recommended operating conditions at the V chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V respective V and V voltage levels ...
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Table 10: Differential I/O Standard DC Input and Output Levels V ID mV, mV, I/O Standard Min Max (2)(3) LVDS_33 100 600 (2)(3) LVDS_25 100 600 (2)(3) BLVDS_25 100 – MINI_LVDS_33 200 600 MINI_LVDS_25 200 600 (2)(3) LVPECL_33 100 1000 ...
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Read Endurance Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For more information, see the Spartan-6 FPGA Configuration User Guide. Table 11: eFUSE Read Endurance Symbol DNA_CYCLES ...
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Table 14: GTP Transceiver Current Supply (per Lane) Symbol I GTP transceiver internal analog supply current MGTAVCC I GTP transmitter termination supply current MGTAVTTTX I GTP receiver termination supply current MGTAVTTRX I GTP transmitter and receiver PLL supply current MGTAVCCPLL ...
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GTP Transceiver DC Input and Output Levels Table 16 summarizes the DC output specifications of the GTP transceivers in Spartan-6 FPGAs. ended output voltage swing. Figure 2 Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further details. Table 16: ...
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Table 17: GTP Transceiver Clock DC Input Level Specification Symbol V Differential peak-to-peak input voltage IDIFF R Differential input resistance IN C Required external AC coupling capacitor EXT GTP Transceiver Switching Characteristics Consult the Spartan-6 FPGA GTP Transceivers User Guide ...
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Table 21: GTP Transceiver User Clock Switching Characteristics Symbol Description F TXOUTCLK maximum frequency TXOUT F RXRECCLK maximum frequency RXREC T RXUSRCLK maximum frequency RX T RXUSRCLK2 maximum frequency RX2 T TXUSRCLK maximum frequency TX T TXUSRCLK2 maximum frequency TX2 ...
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Table 23: GTP Transceiver Receiver Switching Characteristics Symbol T Time for RXELECIDLE to respond to loss or restoration of data RXELECIDLE R OOB detect threshold peak-to-peak XOOBVDPP R Receiver spread-spectrum tracking XSST R Run length (CID) XRL Data/REFCLK PPM offset ...
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Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as ...
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Switching Characteristics All values represented in this data sheet are based on these speed specifications: v1.17 for -3, -3N, and -2; and v1.06 for -1L. Switching characteristics are specified on a per-speed- grade basis and can be designated as Advance, ...
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Production Silicon and ISE Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent ...
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Table 28: IOB Switching Characteristics I/O Standard LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 LVPECL_33 LVPECL_25 RSDS_33 (point to point) RSDS_25 (point to point) TMDS_33 PPDS_33 PPDS_25 PCI33_3 PCI66_3 DISPLAY_PORT I2C SMBUS SDIO MOBILE_DDR HSTL_I HSTL_II HSTL_III HSTL_I _18 HSTL_II _18 HSTL_III ...
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Table 28: IOB Switching Characteristics (Cont’d) I/O Standard DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL15_II DIFF_MOBILE_DDR LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO LVTTL, QUIETIO ...
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Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Slow LVCMOS33, Fast LVCMOS33, Fast LVCMOS33, Fast ...
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Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS18, QUIETIO LVCMOS18, QUIETIO LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow LVCMOS18, Slow ...
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Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, QUIETIO LVCMOS15, Slow LVCMOS15, Slow ...
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Table 28: IOB Switching Characteristics (Cont’d) I/O Standard LVCMOS12, QUIETIO LVCMOS12, QUIETIO LVCMOS12, QUIETIO LVCMOS12, Slow LVCMOS12, Slow LVCMOS12, Slow LVCMOS12, Slow LVCMOS12, Slow ...
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I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, ...
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Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately ...
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Table 31: Output Delay Measurement Methodology (Cont’d) Description SSTL, Class II, 2.5V SSTL, Class II, 1.5V LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V BLVDS (Bus LVDS), 2.5V Mini-LVDS, 2.5V & 3.3V RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, ...
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Table 32: Spartan-6 FPGA V /GND Pairs per Bank CCO Package Devices TQG144 LX CPG196 LX CSG225 LX FT(G)256 LX LX CSG324 LXT LX CSG484 LXT LX FG(G)484 LXT LX45 FG(G)676 LX75, LX100, LX150 LXT LX FG(G)900 LXT DS162 (v2.0) ...
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Table 33: SSO Limit per V /GND Pair CCO V I/O Standard CCO 1.2V LVCMOS12, LVCMOS12_JEDEC DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SSO Limit per V All TQG144, CPG196, Drive ...
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Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVCMOS15, LVCMOS15_JEDEC 1.5V HSTL_I HSTL_II HSTL_III DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III (3) SSTL_15_II (3) DIFF_SSTL_15_II DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC ...
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Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVCMOS18, LVCMOS18_JEDEC 1.8V HSTL_I_18 HSTL_II_18 HSTL_III_18 DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 (3) MOBILE_DDR (3) DIFF_MOBILE_DDR (3) SSTL_18_I (3) SSTL_18_II (3) DIFF_SSTL_18_I (3) DIFF_SSTL_18_II DS162 (v2.0) March 31, 2011 ...
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Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVCMOS25 2.5V (3) SSTL_2_I (3) SSTL_2_II (3) DIFF_SSTL_2_I (3) DIFF_SSTL_2_II DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics ...
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Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO 3.3V LVCMOS33 DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SSO Limit per V All TQG144, CPG196, Drive ...
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Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVTTL 3.3V PCI33_3 PCI66_3 SSTL_3_I SSTL_3_II DIFF_SSTL_3_I DIFF_SSTL_3_II SDIO DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics SSO ...
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Table 33: SSO Limit per V /GND Pair (Cont’d) CCO V I/O Standard CCO LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 RSDS_33 Various RSDS_25 TMDS_33 PPDS_33 PPDS_25 DISPLAY_PORT I2C SMBUS Notes: 1. SSO limits greater than the number of I/O per V ...
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Input/Output Logic Switching Characteristics Table 34: ILOGIC2 Switching Characteristics Symbol Setup/Hold T /T CE0 pin Setup/Hold with respect to CLK ICE0CK ICKCE0 pin Setup/Hold with respect to CLK ISRCK ICKSR pin Setup/Hold with respect ...
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Input Serializer/Deserializer Switching Characteristics Table 36: ISERDES2 Switching Characteristics Symbol Setup/Hold for Control Lines BITSLIP pin Setup/Hold with respect to CLKDIV ISCCK_BITSLIP ISCKC_BITSLIP pin Setup/Hold with respect to CLK ISCCK_CE ISCKC_CE Setup/Hold for ...
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Input/Output Delay Switching Characteristics Table 38: IODELAY2 Switching Characteristics Symbol CAL pin Setup/Hold with respect to CK IODCCK_CAL IODCKC_CAL pin Setup/Hold with respect to CK IODCCK_CE IODCKC_CE INC pin Setup/Hold ...
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CLB Switching Characteristics (SLICEM Only) Table 39: CLB Switching Characteristics (SLICEM Only) Symbol Combinatorial Delays T An – Dn LUT inputs outputs ILO An – Dn LUT inputs through F7AMUX/F7BMUX to AMUX/CMUX output T An – ...
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CLB Distributed RAM Switching Characteristics (SLICEM Only) Table 40: CLB Distributed RAM Switching Characteristics (SLICEM Only) Symbol Sequential Delays T Clock to A – D outputs SHCKO Clock to A – D outputs (direct output path) Setup and Hold Times ...
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Block RAM Switching Characteristics Table 42: Block RAM Switching Characteristics Symbol Block RAM Clock to Out Delays T Clock CLK to DOUT output (without output register) RCKO_DO T Clock CLK to DOUT output (with output register) RCKO_DO_REG Setup and Hold ...
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DSP48A1 Switching Characteristics Table 43: DSP48A1 Switching Characteristics Symbol Setup and Hold Times of Data/Control Pins to the Input Register Clock input to A1 register CLK DSPDCK_A_A1REG T DSPCKD_A_A1REG input to B1 register CLK ...
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Table 43: DSP48A1 Switching Characteristics (Cont’d) Symbol Clock to Out from Output Register Clock to Output Pin T CLK (PREG output DSPCKO_P_PREG Clock to Out from Pipeline Register Clock to Output Pins T CLK (MREG output ...
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Table 44: Device DNA Interface Port Switching Characteristics Symbol T Setup time on SHIFT before the rising edge of CLK DNASSU T Hold time on SHIFT after the rising edge of CLK DNASH T Setup time on DIN before the ...
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Configuration Switching Characteristics Table 46: Configuration Switching Characteristics Symbol Power-up Timing Characteristics (2) T PROGRAM_B Latency PL (2) T Power-on-Reset POR T PROGRAM_B Pulse Width PROGRAM Slave Serial Mode Programming Switching T /T DIN Setup/Hold, slave mode DCCK CCKD T ...
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Table 46: Configuration Switching Characteristics Symbol T /T Setup/Hold on D[15:0] data input pins BPIDCC BPICCD SPI Master Flash Mode Programming Switching T /T DIN, MISO0, MISO1, MISO2, MISO3, Setup/Hold SPIDCC SPIDCCD before/after the rising CCLK edge T Master SPI ...
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Clock Buffers and Networks Table 47: Global Clock Switching Characteristics Symbol T S pin Setup to I0/I1 inputs GSI T BUFGMUX delay from I0/ GIO Maximum Frequency F Global clock tree (BUFG) MAX Table 48: Input/Output Clock Switching ...
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PLL Switching Characteristics Table 50: PLL Specification Symbol F Maximum Input Clock Frequency from I/O Clock INMAX Maximum Input Clock Frequency from Global Clock F Minimum Input Clock Frequency INMIN F Maximum Input Clock Period Jitter INJITTER F Allowable Input ...
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DCM Switching Characteristics Table 51: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL) Symbol Input Frequency Ranges CLKIN_FREQ_DLL Frequency of the CLKIN clock input when the CLKDV output is not used. Frequency of the CLKIN clock input when ...
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Table 52: Switching Characteristics for the Delay-Locked Loop (DLL) Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs. CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs. CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs. CLKOUT_FREQ_DV Frequency for ...
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Table 52: Switching Characteristics for the Delay-Locked Loop (DLL) Symbol (3) LOCK_DLL When using the DLL alone: The time from deassertion at the DCM’s reset input to the rising transition at its LOCKED output. When the DCM is locked, the ...
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Table 54: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP Symbol Output Frequency Ranges Frequency for the CLKFX and CLKOUT_FREQ_FX CLKFX180 outputs (2)(3) Output Clock Jitter Period jitter at the CLKFX and CLKFX180 outputs. When CLKIN < 20 ...
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Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN) Symbol Output Frequency Ranges (DCM_CLKGEN) CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs CLKOUT_FREQ_FXDV Frequency for the CLKFXDV output (2)(3) Output Clock Jitter CLKOUT_PER_JITT_FX Period jitter at the CLKFX ...
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Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN) Symbol Spread Spectrum F Frequency of the CLKIN input for CLKIN_FIXED_SPREAD_ fixed spread spectrum SPECTRUM (SPREAD_SPECTRUM = CENTER_LOW_SPREAD/ CENTER_HIGH_SPREAD) (6) T Spread at the CLKFX output for CENTER_LOW_SPREAD fixed ...
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Table 57: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode Symbol Phase Shifting Range When CLKIN < 60 MHz, the maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period ...
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Spartan-6 Device Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 61 through Table 67. Values are expressed in nanoseconds unless otherwise noted. Table ...
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Table 62: Global Clock Input to Output Delay With DCM in System-Synchronous Mode Symbol LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode. T Global Clock and OUTFF with DCM ...
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Table 63: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode Symbol LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode. T Global Clock and OUTFF with DCM ...
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Table 65: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode Symbol LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode. T Global Clock and OUTFF with PLL ...
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Table 67: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode Symbol LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode and PLL in DCM2PLL Mode. ...
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Spartan-6 Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 68 through Table 74. Values are expressed in nanoseconds unless otherwise noted. Table ...
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Table 69: Global Clock Setup and Hold With DCM in System-Synchronous Mode Symbol Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard Delay Global Clock and IFF PSDCM PHDCM System-Synchronous Mode ...
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Table 70: Global Clock Setup and Hold With DCM in Source-Synchronous Mode Symbol Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard Delay Global Clock and IFF PSDCM0 PHDCM0 Source-Synchronous Mode ...
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Table 71: Global Clock Setup and Hold With PLL in System-Synchronous Mode Symbol Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard Delay Global Clock and IFF PSPLL PHPLL System-Synchronous Mode ...
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Table 72: Global Clock Setup and Hold With PLL in Source-Synchronous Mode Symbol Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard Delay Global Clock and IFF PSPLL0 PHPLL0 Source-Synchronous Mode ...
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Table 73: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode Symbol Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard Delay Global Clock and IFF PSDCMPLL T System-Synchronous ...
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Table 74: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode Symbol Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin, situations where clock and data inputs conform to different standards, adjust ...
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Source-Synchronous Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Spartan-6 FPGA source-synchronous transmitter and receiver data-valid windows. Table 75: Duty Cycle Distortion and Clock-Tree Skew Symbol Description T Global Clock Tree Duty ...
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Table 75: Duty Cycle Distortion and Clock-Tree Skew (Cont’d) Symbol Description T I/O clock tree skew across one clock region BUFIOSKEW Notes: 1. LXT devices are not available with a -1L speed grade. The LX4 is not available in -3N ...
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Table 76: Package Skew Symbol T Package Skew PKGSKEW DS162 (v2.0) March 31, 2011 Preliminary Product Specification Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T www.xilinx.com ...
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Table 76: Package Skew (Cont’d) Symbol T Package Skew PKGSKEW Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball. 2. Some of these devices ...
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Table 78: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Using BUFIO2 Symbol Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO2 T /T IFF setup/hold using BUFIO2 clock PSCS PHCS Pin-to-Pin Clock-to-Out Using BUFIO2 T OFF ...
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Revision History The following table shows the revision history for this document. Date Version 06/24/09 1.0 Initial Xilinx release. 08/26/09 1.1 Added V V BATT XC6SLX4 in Table 24 values for T to Table 46, page 46 T SMCKCSO (DRP) ...
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Date Version 06/14/10 1.5 In Table delineation, revised I DIFF_MOBILE_DDR to Table descriptions and added data to Applications section in speed specification v1.08. In Updated the maximum I/O pairs per bank in in Table value, added T F RBCCK on ...
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Date Version 01/10/11 1.11 Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in Table 27 grades. Added note 3 to software with speed specification v1.06. Revised -3N definition throughout the document. Added Note 4 to Updated ...