XA3S1000-4FGG456I Xilinx Inc, XA3S1000-4FGG456I Datasheet
XA3S1000-4FGG456I
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XA3S1000-4FGG456I Summary of contents
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... XA3S200 200K 4,320 24 XA3S400 400K 8,064 32 XA3S1000 1M 17,280 48 XA3S1500 1.5M 29,952 64 Notes convention, one Kb is equivalent to 1,024 bits. © 2004–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries ...
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R ♦ Fast look-ahead carry logic ♦ Dedicated multipliers ♦ JTAG logic compatible with IEEE 1149.1/1532 • SelectRAM™ hierarchical memory ♦ 576 Kbits of total block RAM ♦ 208 Kbits of total distributed ...
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R Notes: 1. The XA3S50 has only the block RAM column on the far left. Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. Before powering ...
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R Table 2: Signal Standards Supported by the Spartan-3 Family Standard Description Category Single-Ended GTL Gunning Transceiver Logic HSTL High-Speed Transceiver Logic LVCMOS Low-Voltage CMOS LVTTL Low-Voltage Transistor-Transistor Logic PCI Peripheral Component Interconnect SSTL Stub Series Terminated Logic Differential LDT ...
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... R Table 3: Spartan-3 XA I/O Chart VQG100 Device Grade User Diff XA3S50 I XA3S200 I XA3S400 I XA3S1000 I XA3S1500 Notes: 1. All device options listed in a given package column are pin-compatible. DC Specifications Table 4: General Recommended Operating Conditions Symbol Description T Junction temperature J V Internal supply voltage CCINT V Output driver supply voltage ...
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... Device Type Speed Grade Temperature Range Figure 2: Spartan-3 BGA Package Marking Example for Part Number XA3S1000-4 FTG256Q Spartan-3 FPGAs are available in Pb-free packaging options for all device/package combinations. The Pb-free packages include a special “G” character in the ordering code. DS314 (v1.3) June 18, 2009 ...
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... Table 4, and 11/28/06 1.2.1 Changed order of explanations in 11/12/07 1.2.2 Changed all values for the Block RAM (bits) column and two values for the XA3S1000 row in 01/25/08 1.2.3 Changed XA3S1500 Q-Grade Maximum in 06/18/09 1.3 Added UG331 and UG332 to DS314 (v1.3) June 18, 2009 ...
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R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ...