XC5VFX30T-1FFG665C Xilinx Inc, XC5VFX30T-1FFG665C Datasheet - Page 57

• Manufacturer Part Number: XC5VFX30T-1FFG665C
• Description: IC FPGA VIRTEX-5FX 30K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FFG665C

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Core Supply Voltage Range: 0.95V To 1.05V
• Operating Frequency Max: 600MHz
• Operating: RoHS Compliant
• Package: 665FCBGA
• Family Name: Virtex®-5
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2506752
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1583; XC5VFX30T-1FFG665C

DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
Outputs Clocks (Low Frequency Mode)
F
F
F
F
F
F
F
F
Input Clocks (Low Frequency Mode)
F
F
F
F
F
F
Outputs Clocks (High Frequency Mode)
F
F
F
F
F
F
F
F
Input Clocks (High Frequency Mode)
F
F
F
F
F
F
1XLFMSMIN
1XLFMSMAX
2XLFMSMIN
2XLFMSMAX
DVLFMSMIN
DVLFMSMAX
FXLFMSMIN
FXLFMSMAX
DLLLFMSMIN
DLLLFMSMAX
CLKINLFFXMSMIN
CLKINLFFXMSMAX
PSCLKLFMSMIN
PSCLKLFMSMAX
1XHFMSMIN
1XHFMSMAX
2XHFMSMIN
2XHFMSMAX
DVHFMSMIN
DVHFMSMAX
FXHFMSMIN
FXHFMSMAX
DLLHFMSMIN
DLLHFMSMAX
CLKINHFFXMSMIN
CLKINHFFXMSMAX
PSCLKHFMSMIN
PSCLKHFMSMAX
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
Symbol
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
CLKIN (using DLL outputs)
CLKIN (using DFS outputs only)
PSCLK
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Description
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1, 3, 4)
(1, 3, 4)
(2, 3, 4)
(2, 3, 4)
150.00
300.00
100.00
180.00
150.00
180.00
550.00
120.00
550.00
240.00
550.00
366.67
140.00
400.00
120.00
550.00
400.00
550.00
32.00
64.00
32.00
32.00
25.00
1.00
1.00
1.00
2.0
7.5
-3
Speed Grade
135.00
270.00
160.00
135.00
160.00
500.00
120.00
500.00
240.00
500.00
333.34
140.00
375.00
120.00
500.00
375.00
500.00
32.00
64.00
90.00
32.00
32.00
25.00
1.00
1.00
1.00
2.0
7.5
-2
120.00
240.00
140.00
120.00
140.00
450.00
120.00
450.00
240.00
450.00
300.00
140.00
350.00
120.00
450.00
350.00
450.00
32.00
64.00
80.00
32.00
32.00
25.00
1.00
1.00
1.00
2.0
7.5
-1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
KHz
KHz
57