XC5VLX50T-1FFG1136C Xilinx Inc, XC5VLX50T-1FFG1136C Datasheet

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-1FFG1136C

Manufacturer Part Number
XC5VLX50T-1FFG1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-1FFG1136C

Total Ram Bits
2211840
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
No. Of Logic Blocks
7200
No. Of Gates
50000
Family Type
Virtex-5 LXT
No. Of Speed Grades
1
No. Of I/o's
480
Clock Management
PLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1564
XCN07026 (v1.0.3) July 29, 2009
Overview
The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select
Virtex®-5 LXT and SXT FPGA devices.
Description
This notification includes the following changes to be implemented:
Key Dates and Ordering Information
Key dates for this notice are detailed in Key Dates for Package Transition.
XCN07026 (v1.0.3) July 29, 2009
Table 1: Key Dates for Package Transition
*
**
If a qualification of the new material is necessary, customers can order samples of Step 1 10-layer devices by appending "S1" to the end of
standard part numbers from January 1, 2008 through April 30, 2008.
Starting from May 1, 2008, orders using standard part numbers will receive devices in either Step 0 or Step 1, 8-layer or 10-layer.
Introduction of Step 1: Specific LXT and SXT devices will begin transitioning to a new mask revision, designated as
Step 1, which will improve the CDM ESD performance. The current production silicon is designated as Step 0. The
Step 1 devices are form, fit, function, and bitstream compatible with Step 0. (For information on the Xilinx Stepping
Methodology, see
Package change: LXT and SXT devices in packages greater than 1000 pins will begin transitioning to 10-layer
package substrates, as part of the Xilinx material standardization for the Virtex-5 FPGA family. This change is
backward-compatible with current production devices. This change will not affect the current package outline drawing.
December 31, 2007
Notification Date
© Copyright 2007 - 2009 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands
Xilinx Answer
included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
20947).
January 1, 2008 - April 30, 2008
Transition Period*
www.xilinx.com
Transition to Step 1 and New
Package Substrate for Select
Virtex-5 LXT and SXT FPGA
Devices
(Cross-shipping starts)
Implementation Date**
Product/Process Change Notice
May 1, 2008
1

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XC5VLX50T-1FFG1136C Summary of contents

Page 1

XCN07026 (v1.0.3) July 29, 2009 Overview The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select Virtex®-5 LXT and SXT FPGA devices. Description This notification includes the following changes to ...

Page 2

... During Transition Period After Transition Period Example Ordering Example Ordering Part No. Part No. (Jan 2007 to April 2008) (after April 2008) XC5VLX50T-1FF1136C XC5VLX50T-1FF1136C (Step 0 or Step 1, (Step 0, 8-Layer) 8-Layer or 10-Layer) XC5VLX50T-1FF1136CS1 XC5VLX50T-1FF1136CS1 (Step 1, 10-Layer) (Step 1, 10-Layer) XC5VLX30T-1FF665C XC5VLX30T-1FF665C (Step 0 or Step 1, 8- ...

Page 3

Response Note: In accordance with JESD46-C, this change is deemed accepted by the customer if no acknowledgement is received within 30 days from this notice. No response is required by this notice. For additional information or questions, please contact Important ...

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