XC5VLX50T-2FF1136C Xilinx Inc, XC5VLX50T-2FF1136C Datasheet - Page 48

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VLX50T-2FF1136C

Manufacturer Part Number
XC5VLX50T-2FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr

Specifications of XC5VLX50T-2FF1136C

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

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Price
Part Number:
XC5VLX50T-2FF1136C
Manufacturer:
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Quantity:
10 000
Part Number:
XC5VLX50T-2FF1136C
Manufacturer:
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Quantity:
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Part Number:
XC5VLX50T-2FF1136C
Quantity:
220
Table 68: Block RAM and FIFO Switching Characteristics (Cont’d)
DSP48E Switching Characteristics
Table 69: DSP48E Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Reset Delays
T
Maximum Frequency
F
F
F
F
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
TDSPDCK_CC/TDSPCKD_CC
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
TDSPDCK_CP/TDSPCKD_CP
TDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B, CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
TDSPCCK_CECC/TDSPCKC_CECC
RCO_FLAGS
MAX
MAX_CASCADE
MAX_FIFO
MAX_ECC
TRACE will report all of these parameters as T
T
These parameters also apply to synchronous FIFO with DO_REG = 0.
T
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
T
The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
T
These parameters also apply to RDEN.
T
RCKO_DOR
RCKO_DO
RCKO_FLAGS
RCKO_POINTERS
RCKO_DI
RCO_FLAGS
Symbol
includes both A and B inputs as well as the parity inputs of A and B.
includes T
includes T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
includes the following parameters: T
includes both T
RCKO_DOP
RCKO_DOW
Symbol
as well as the B port equivalent timing parameters.
, T
RCKO_RDCOUNT
Reset RST to FIFO Flags/Pointers
Block RAM in all modes
Block RAM in cascade configuration
FIFO in all modes
Block RAM and FIFO in ECC configuration
RCKO_DOPR
RCKO_DO
, and T
and T
RCKO_AEMPTY
RCKO_DOPW
RCKO_WRCOUNT.
.
Description
{A, B, ACIN, BCIN} input to {A, B}
register CLK
C input to C register CLK
{A, B, ACIN, BCIN} input to M register
CLK
{A, B, ACIN, BCIN} input to P register
CLK using multiplier
{A, B, ACIN, BCIN} input to P register
CLK not using multiplier
C input to P register CLK
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to P register CLK
{CEA1, CEA2A, CEB1B, CEB2B} input
to {A, B} register CLK
CEC input to C register CLK
www.xilinx.com
, T
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
as well as the B port equivalent timing parameters.
RCKO_AFULL
(11)
Description
, T
RCKO_EMPTY
, T
RCKO_FULL
1.10
550
500
550
415
-3
, T
Speed Grade
RCKO_RDERR
–0.30
–0.10
–0.13
0.17
0.17
0.14
0.26
1.30
0.19
2.39
1.35
1.30
1.06
0.11
0.24
0.21
0.19
0.17
-3
1.26
500
450
500
375
-2
Speed
–0.30
–0.10
–0.13
0.21
0.23
0.16
0.31
1.44
0.19
2.74
1.54
1.42
1.17
0.11
0.28
0.25
0.21
0.21
, T
-2
RCKO_WRERR.
1.48
400
450
450
325
-1
–0.30
–0.10
–0.13
0.26
0.30
0.20
0.37
1.71
0.19
3.25
1.83
1.70
1.31
0.11
0.33
0.31
0.26
0.28
-1
ns, Max
Units
MHz
MHz
MHz
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
48

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