XC4VLX60-11FFG1148I

Manufacturer Part NumberXC4VLX60-11FFG1148I
DescriptionIC FPGA VIRTEX-4 LX 60K 1148FBGA
ManufacturerXilinx Inc
SeriesVirtex™-4
XC4VLX60-11FFG1148I datasheets

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Specifications of XC4VLX60-11FFG1148I

Number Of Logic Elements/cells59904Number Of Labs/clbs6656
Total Ram Bits2949120Number Of I /o640
Voltage - Supply1.14 V ~ 1.26 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case1148-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Architectural Description: Virtex-4 FPGA Array Overview
Virtex-4 devices are user-programmable gate arrays with
various configurable elements and embedded cores opti-
mized for high-density and high-performance system
designs. Virtex-4 devices implement the following function-
ality:
•
I/O blocks provide the interface between package pins
and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by
programmable I/O blocks (IOBs). The IOBs are
enhanced for source-synchronous applications.
Source-synchronous optimizations include per-bit
deskew, data serializer/deserializer, clock dividers, and
dedicated local clocking resources.
•
Configurable Logic Blocks (CLBs), the basic logic
elements for Xilinx FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and
SRL16 shift register capability.
•
Block RAM modules provide flexible 18Kbit true
dual-port RAM, that are cascadable to form larger
memory blocks. In addition, Virtex-4 FPGA block RAMs
contain optional programmable FIFO logic for
increased device utilization.
•
Cascadable embedded XtremeDSP slices with 18-bit x
18-bit dedicated multipliers, integrated Adder, and
48-bit accumulator.
Virtex-4 FPGA Features
This section briefly describes the features of the Virtex-4 family of FPGAs.
Input/Output (SelectIO) Blocks
IOBs are programmable and can be categorized as follows:
•
Programmable single-ended or differential (LVDS)
operation
•
Input block with an optional single data rate (SDR) or
double data rate (DDR) register
•
Output block with an optional SDR or DDR register
•
Bidirectional block
•
Per-bit deskew circuitry
•
Dedicated I/O and regional clocking resources
•
Built in data serializer/deserializer
The IOB registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended standards:
•
LVTTL
•
LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
•
PCI (33 and 66 MHz)
•
PCI-X
•
GTL and GTLP
DS112 (v3.1) August 30, 2010
Product Specification
•
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock
multiplication/division, and coarse-/fine-grained clock
phase shifting.
Additionally, FX devices support the following embedded
system functionality:
•
Integrated high-speed serial transceivers enable data
rates up to 6.5 Gb/s per channel.
•
Embedded IBM PowerPC 405 Processor RISC CPU
(up to 450 MHz) with the auxiliary processor unit
interface
•
10/100/1000 Ethernet media-access control (EMAC)
cores.
The general routing matrix (GRM) provides an array of rout-
ing switches between each component. Each programma-
ble element is tied to a switch matrix, allowing multiple
connections to the general routing matrix. The overall pro-
grammable interconnection is hierarchical and designed to
support high-speed designs.
All
programmable
elements,
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
•
HSTL 1.5V and 1.8V (Class I, II, III, and IV)
•
SSTL 1.8V and 2.5V (Class I and II)
The DCI I/O feature can be configured to provide on-chip
termination for each single-ended I/O standard and some
differential I/O standards.
The IOB elements also support the following differential sig-
naling I/O standards:
•
LVDS and Extended LVDS (2.5V only)
•
BLVDS (Bus LVDS)
•
ULVDS
•
Hypertransport™
•
Differential HSTL 1.5V and 1.8V (Class II)
•
Differential SSTL 1.8V and 2.5V (Class II)
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Per-bit deskew circuitry allows for programmable signal
delay internal to the FPGA. Per-bit deskew flexibly provides
fine-grained increments of delay to carefully produce a
www.xilinx.com
Virtex-4 Family Overview
including
the
routing
4

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