XCV812E-6BG560C Xilinx Inc, XCV812E-6BG560C Datasheet - Page 38

• Manufacturer Part Number: XCV812E-6BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6BG560C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 404
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Dc: 0325
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent V
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a V
amplifier input signal within a given V
external source must drive all I/O pins configured as a V
input.
IBUF placement restrictions require that any differential
amplifier input signals within a bank be of the same stan-
dard. How to specify a specific location for the IBUF via the
LOC property is described below.
Virtex-E input standards compatibility requirements.
An optional delay element is associated with each IBUF.
When the IBUF drives a flip-flop within the IOB, the delay
element by default activates to ensure a zero hold-time
requirement. The NODELAY=TRUE property overrides this
default.
When the IBUF does not drive a flip-flop within the IOB, the
delay element de-activates by default to provide higher per-
formance. To delay the input signal, activate the delay ele-
ment with the DELAY=TRUE property.
Table 19:
IBUFG
Signals used as high fanout clock inputs to the Virtex-E
device should drive a global clock input buffer (IBUFG) via
an external input port in order to take advantage of one of
the four dedicated global clock distribution networks. The
output of the IBUFG should only drive a CLKDLL,
Module 2 of 4
34
Rule 1
Standards with the same input V
and V
Xilinx Input Standards Compatibility
Requirements
Figure 38: Virtex-E I/O Banks
REF
Bank 0
Bank 5
can be placed within the same bank.
GCLK3
GCLK1
REF
REF
Virtex-E
Device
input. After placing a differential
banks internally. See
GCLK2
GCLK0
Table 19
Bank 1
Bank 4
REF
CCO
ds022_42_012100
bank, the same
summarizes the
, output V
Figure 38
CCO
www.xilinx.com
1-800-255-7778
REF
,
CLKDLLHF, or a BUFG symbol. The generic Virtex-E
IBUFG symbol appears in
The extension to the base name determines which I/O stan-
dard is used by the IBUFG. With no extension specified for
the generic IBUFG symbol, the assumed standard is
LVTTL.
The following list details variations of the IBUFG symbol.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
When the IBUFG symbol supports an I/O standard that
requires a differential amplifier input, the IBUFG automati-
cally configures as a differential amplifier input buffer. The
low-voltage I/O standards with a differential amplifier input
require an external reference voltage input V
The voltage reference signal is “banked” within the Virtex-E
device on a half-edge basis such that for all packages there
are eight independent V
for a representation of the Virtex-E I/O banks. Within each
bank approximately one of every six I/O pins is automati-
cally configured as a V
amplifier input signal within a given V
external source must drive all I/O pins configured as a V
input.
IBUFG placement restrictions require any differential ampli-
fier input signals within a bank be of the same standard. The
LOC property can specify a location for the IBUFG.
Figure 39: Virtex-E Global Clock Input Buffer (IBUFG)
IBUFG
IBUFG_LVCMOS2
IBUFG_PCI33_3
IBUFG_PCI66_3
IBUFG_GTL
IBUFG_GTLP
IBUFG_HSTL_I
IBUFG_HSTL_III
IBUFG_HSTL_IV
IBUFG_SSTL3_I
IBUFG_SSTL3_II
IBUFG_SSTL2_I
IBUFG_SSTL2_II
IBUFG_CTT
IBUFG_AGP
IBUFG_LVCMOS18
IBUFG_LVDS
IBUFG_LVPECL
I
REF
REF
IBUFG
Symbol
Figure
DS025-2 (v2.3) November 19, 2002
input. After placing a differential
banks internally. See
x133_03_111699
39.
O
REF
bank, the same
REF
.
Figure 38
REF
R