AT40K10-2CQC Atmel, AT40K10-2CQC Datasheet - Page 19

• Manufacturer Part Number: AT40K10-2CQC
• Description: IC FPGA 10K GATES 160PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K10-2CQC

• Number Of Logic Elements/cells: 576
• Total Ram Bits: 4608
• Number Of I /o: 130
• Number Of Gates: 20000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 160-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K102CQC

Primary, Secondary and
Corner I/Os
Primary I/O
Secondary I/O
Corner I/O
0896C–FPGA–04/02
The AT40K/AT40KLV has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner
I/O. Every edge cell except corner cells on the AT40K/AT40KLV has access to one Pri-
mary I/O and two Secondary I/Os.
Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and
from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It
also connects into the repeaters on the row immediately above and below the adjacent
core cell. In addition, each Primary I/O also connects into the busing network of the
three nearest edge cells. This is an extremely powerful feature, as it provides logic cells
toward the center of the array with fast access to I/Os via local and express buses. It can
be seen from the diagram that a given Primary I/O can be accessed from any logic cell
on three separate rows or columns of the FPGA. See Figures 12a on page 20 and 13a
on page 21.
Every logic cell at the edge of the FPGA array has two direct diagonal connections to a
Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O
connects on the diagonal inputs to the cell above and the cell below. It also connects to
the repeater of the cell above and below. In addition, each Secondary I/O also connects
into the busing network of the two nearest edge cells. This is an extremely powerful fea-
ture, as it provides logic cells toward the center of the array with fast access to I/Os via
local and express buses. It can be seen from the diagram that a given Secondary I/O
can be accessed from any logic cell on two rows or columns of the FPGA. See Figure
12b on page 20 and Figure 13b.
Logic cells at the corner of the FPGA array have direct-connect access to five separate
I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary
I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40K/AT40KLV
FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can
be accessed both from the corner logic cell and the horizontal and vertical busing net-
works running along the edges of the array. This means that many different edge logic
cells can access the Corner I/Os. See Figure 14 on page 22.
AT40K/AT40KLV Series FPGA
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