AT40K40LV-3BGC Atmel, AT40K40LV-3BGC Datasheet - Page 4

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AT40K40LV-3BGC

Manufacturer Part Number
AT40K40LV-3BGC
Description
IC FPGA 3.3V 2304 CELL 352BGA
Manufacturer
Atmel
Series
AT40K/KLVr
Datasheet

Specifications of AT40K40LV-3BGC

Number Of Logic Elements/cells
2304
Total Ram Bits
18432
Number Of I /o
289
Number Of Gates
50000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
352-LBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Labs/clbs
-
Other names
AT40K40LV3BGC
Figure 2. Floorplan (representative portion)
The Busing Network
Figure 3 depicts one of five identical busing planes. Each
plane has 3 bus resources: a local-bus resource (the mid-
dle bus) and 2 express-bus resources. Bus resources are
connected via repeaters. Each repeater has connections to
two adjacent local-bus segments and two express-bus seg-
ments. Each local-bus segment spans four cells and con-
nects to consecutive repeaters. Each express-bus segment
spans eight cells and “leapfrogs” or bypasses a repeater.
Repeaters regenerate signals and can connect any bus to
4
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
AT40K
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RV
RH
RV
RV
RV
RV
RV
RV
RV
RV
= Vertical Repeater
= Horizontal Repeater
= Cell
RV
RV
RV
RV
any other bus (all pathways are legal) on the same plane.
Although not shown, a local bus can bypass a repeater via
a programmable pass gate allowing long on-chip three
state buses to be created. Local/Local turns are imple-
mented through pass gates in the cell-bus interface (see
following page). Express/Express turns are implemented
through separate pass gates distributed throughout the
array.
RV
RV
RV
RV
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RV
RAM
RAM
RAM
RAM
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH
RH

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