AT40K40LV-3BGI Atmel, AT40K40LV-3BGI Datasheet - Page 3

• Manufacturer Part Number: AT40K40LV-3BGI
• Description: IC FPGA 3.3V 2304 CELL 352BGA
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K40LV-3BGI

• Number Of Logic Elements/cells: 2304
• Total Ram Bits: 18432
• Number Of I /o: 289
• Number Of Gates: 50000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K40LV3BGI

Cache Logic Design
Automatic Component
Generators
0896CS–FPGA–05/02
The AT40K/AT40KLV, AT6000 and FPSLIC families are capable of implementing
Cache Logic (dynamic full/partial logic reconfiguration, without loss of data, on-the-fly)
for building adaptive logic and systems. As new logic functions are required, they can be
loaded into the logic cache without losing the data already there or disrupting the opera-
tion of the rest of the chip; replacing or complementing the active logic. The
AT40K/AT40KLV can act as a reconfigurable coprocessor.
The AT40K/AT40KLV FPGA family is capable of implementing user-defined, automati-
cally generated, macros in multiple designs; speed and functionality are unaffected by
the macro orientation or density of the target device. This enables the fastest, most pre-
dictable and efficient FPGA design approach and minimizes design risk by reusing
already proven functions. The Automatic Component Generators work seamlessly with
industry standard schematic and synthesis tools to create the fastest, most efficient
designs available.
The patented AT40K/AT40KLV series architecture employs a symmetrical grid of small
yet powerful cells connected to a flexible busing network. Independently controlled
clocks and resets govern every column of cells. The array is surrounded by programma-
ble I/O.
Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to
2,304 registers. Pin locations are consistent throughout the AT40K/AT40KLV series for
easy design migration in the same package footprint. The AT40K/AT40KLV series
FPGAs utilize a reliable 0.6µ single-poly, CMOS process and are 100% factory-tested.
Atmel’s PC- and workstation-based integrated development system (IDS) is used to cre-
ate AT40K/AT40KLV series designs. Multiple design entry methods are supported.
The Atmel architecture was developed to provide the highest levels of performance,
functional density and design flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean functions of (the same) three
inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the functionality in each cell. A simple,
high-speed busing network provides fast, efficient communication over medium and
long distances.
For a complete version of this datasheet, refer to the FPGA section of the Atmel web
site, www.atmel.com.
AT40K/AT40KLV Series FPGA
3