AT40K40LV-3EQC Atmel, AT40K40LV-3EQC Datasheet - Page 30

• Manufacturer Part Number: AT40K40LV-3EQC
• Description: IC FPGA 3.3V 2304 CELL 240PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K40LV-3EQC

• Number Of Logic Elements/cells: 2304
• Total Ram Bits: 18432
• Number Of I /o: 193
• Number Of Gates: 50000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 240-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K40LV3EQC

AC Timing Characteristics - 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Notes:
30
Cell Function
Async RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
Sync RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Write/Read
Read
Read
Read
1. CMOS buffer delays are measured from a V
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer Software.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WECYC
WEL
WEH
setup
hold
setup
hold
hold
PD
PD
PZX
PXZ
CYC
CLKL
CLKH
setup
hold
setup
hold
setup
hold
PD
PD
PD
PZX
PXZ
(max)
(max)
(max)
(max)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(max)
(max)
(max)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
AT40K
CC
CC
= 3.6V, temperature = 0 C
= 3.0V, temperature = 70 C
Path
cycle time
we
we
wr addr setup-> we
wr addr hold -> we
din setup -> we
din hold -> we
oe hold -> we
din -> dout
rd addr -> dout
oe -> dout
oe -> dout
cycle time
clk
clk
we setup-> clk
we hold -> clk
wr addr setup-> clk
wr addr hold -> clk
wr data setup-> clk
wr data hold -> clk
din -> dout
clk -> dout
rd addr -> dout
oe -> dout
oe -> dout
IH
of 1/2 V
CC
at the pad to the internal V
14.0
12.1
12.0
12.1
4.01
6.0
6.0
5.3
0.0
6.0
0.0
0.0
9.7
4.2
3.5
6.0
6.0
3.2
0.0
6.0
0.0
3.0
0.0
9.9
9.7
3.5
-4
12.0
12.0
5.0
5.0
5.3
0.0
5.0
0.0
0.0
8.7
6.3
2.9
3.5
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
8.7
5.8
6.3
2.9
3.5
-3
IH
at A. The input buffer load is constant.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
pulse width low
pulse width high
rd addr = wr addr
pulse width low
pulse width high
rd addr = wr addr
rd addr = wr addr