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... PC platforms. Popular design entry methods are fully supported, including ABEL, sche- matic capture, VHDL, and Verilog HDL synthesis. Design- ers utilizing logic synthesis can use their existing tools to design with the XC5200 devices. . XC5204 XC5206 256 480 784 3,000 6,000 10,000 ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays XC5200 Family Compared to XC4000/Spartan™ and XC3000 Series For readers already familiar with the XC4000/Spartan and XC3000 FPGA Families, this section describes significant differences between them and the XC5200 ...
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Product Obsolete or Under Obsolescence R XC3000 family: XC5200 devices support an additional pro- gramming mode: Peripheral Synchronous. XC3000 family: The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flip-flops. XC3000 ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays The XC5200 CLB consists of four LCs, as shown in Figure 4. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs ...
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Product Obsolete or Under Obsolescence R single-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained Versa-Block. Throughout the XC5200 interconnect, an effi- cient multiplexing scheme, in combination with three ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays carry out CY_MUX and B3 XOR F2 to any two CY_MUX and B2 ...
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Product Obsolete or Under Obsolescence R tomized RPMs, freeing the designer from the need to become an expert on architectures. cascade out CO DI CY_MUX A15 F4 A14 F3 AND A13 F2 A12 F1 DI CY_MUX F4 A11 F3 A10 ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays can also be independently disabled for any flip-flop. CLR is active High not invertible within the CLB. PAD GR GTS IBUF Figure 8: Schematic Symbols for Global ...
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Product Obsolete or Under Obsolescence R ~100 k "Weak Keeper" Figure 10: 3-State Buffers Implement a Multiplexer Input/Output Blocks User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays non-zero hold, attach a NODELAY attribute or property to the flip-flop or input buffer. IOB Output Signals Output signals can be optionally inverted within the IOB, and pass directly ...
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Product Obsolete or Under Obsolescence R to Vcc. The configurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors value makes them unsuitable as wired-AND pull-up resis- tors. The pull-up resistors ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays To GRM M0-M23 Global Nets 4 4 North 4 South 4 East West 4 Multiplexers Direct North 4 Feedback 4 Direct West 4 4 Direct South Figure 14: VersaBlock ...
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Product Obsolete or Under Obsolescence R Matrix through a hierarchy of different-length metal seg- ments in both the horizontal and vertical directions. A pro- GRM Versa- Block GRM Versa- Block GRM Versa- Block Six Levels of Routing Hierarchy 1 Single-length ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays segments span the width and height of the chip, respectively. Two low-skew horizontal and vertical unidirectional glo- bal-line segments span each row and column of the chip, respectively. Single- ...
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Product Obsolete or Under Obsolescence R . Figure 17: Detail of Programmable Interconnect Associated with XC5200 Series CLB November 5, 1998 (Version 5.2) XC5200 Series Field Programmable Gate Arrays 7 7-97 ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays VersaRing Input/Output Interface The VersaRing, shown in Figure 18, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without ...
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Product Obsolete or Under Obsolescence R senting the decoding of the corresponding state of the boundary-scan internal state machine. IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI M U INSTRUCTION REGISTER ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays XC5200-Series devices can also be configured through the boundary scan logic. See XAPP 017 for more information. Data Registers The primary data register is the boundary scan register. For ...
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Product Obsolete or Under Obsolescence R Optional IBUF BSCAN RESET UPDATE SHIFT TDI TDO TMS DRCK TCK IDLE TDO1 SEL1 From User Logic TDO2 SEL2 Figure 20: Boundary Scan Schematic Example Even if the boundary scan symbol is used in ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays tions During Configuration” on page 124, in the “Configura- tion Timing” section. Table 9: Pin Descriptions I/O I/O During After Pin Name Config. Config. Permanently Dedicated Pins Five or ...
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Product Obsolete or Under Obsolescence R Table 9: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Table 9: Pin Descriptions (Continued) I/O I/O During After Pin Name Config. Config. Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration ...
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Product Obsolete or Under Obsolescence R Master Serial mode generates CCLK and receives the con- figuration data in serial form from a Xilinx serial-configura- tion PROM. CCLK speed is selectable as 1 MHz (default), 6 MHz MHz. Configuration ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Reset Active Low Output 1 1 Active High Output etc . . . . Figure 22: CCLK Generation for XC3000 Master ...
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... Table 12: Internal Configuration Data Structure VersaBlock Device Once per de- vice XC5202 Once per bit- XC5204 stream XC5206 XC5210 XC5215 Bits per Frame = (34 x number of Rows for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill * bits + 24 extended write bits ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Polynomial: X16 + X15 + ...
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Product Obsolete or Under Obsolescence R Length Count Match CCLK DONE I/O XC2000 Global Reset DONE XC3000 I/O Global Reset DONE I/O XC4000E/EX XC5200/ CCLK_NOSYNC GSR Active DONE IN DONE C1 I/O XC4000E/EX XC5200/ CCLK_SYNC GSR Active ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Configuration The length counter begins counting immediately upon entry into the configuration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz ...
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Product Obsolete or Under Obsolescence R When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays DONE High to active user I/O is controlled by an option to the bitstream generation software. Q3 Q1/Q4 STARTUP DONE ...
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Product Obsolete or Under Obsolescence R Note that in XC5200-Series devices, configuration data is not inverted with respect to configuration XC2000 and XC3000 families. Readback of Express mode bitstreams results in data that does not resemble ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Configuration Timing The seven configuration modes are discussed in detail in this section. Timing specifications are included. Slave Serial Mode In Slave Serial mode, an external signal drives the ...
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Product Obsolete or Under Obsolescence R Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays HIGH or 3.3 K N/C LOW DOUT NOTE:M0 can be shorted to Ground if not used as I/O. XC5200 VCC Master Parallel 4.7K INIT PROGRAM D7 ...
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Product Obsolete or Under Obsolescence R . A0-A17 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description Delay to Address valid CCLK Data setup time Data hold time Note power-up, V must rise from 2 ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Synchronous Peripheral Mode Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The first byte of parallel configura- ...
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Product Obsolete or Under Obsolescence R T CCL CCLK INIT BYTE DOUT RDY/BUSY Description INIT (High) setup time setup time hold time CCLK CCLK High time CCLK ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Asynchronous Peripheral Mode Write to FPGA Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being ...
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Product Obsolete or Under Obsolescence R Write to LCA WS/CS0 RS, CS1 D0-D7 CCLK 4 T WTRB RDY/BUSY DOUT Description Effective Write time (CSO, WS=Low; RS, CS1=High Write DIN setup time DIN hold time ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Express Mode Express mode is similar to Slave Serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external ...
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Product Obsolete or Under Obsolescence R CCLK INIT D0-D7 Serial Data Out (DOUT) RDY/BUSY CS1 Description INIT (High) Setup time required DIN Setup time required DIN hold time required CCLK CCLK High time CCLK Low time CCLK ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Table 13. Pin Functions During Configuration CONFIGURATION MODE: <M2:M1:M0> SLAVE MASTER-SER SYN.PERIPH <1:1:1> <0:0:0> <0:1:1> TDI TDI TDI TCK TCK TCK TMS TMS TMS M1 (HIGH) (I) M1 (LOW) ...
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Product Obsolete or Under Obsolescence R Configuration Switching Characteristics T Vcc POR PROGRAM INIT CCLK OUTPUT or INPUT X1532 Master Modes Description Power-On-Reset Program Latency CCLK (output) Delay period (slow) period (fast) Slave and Peripheral Modes Description Power-On-Reset Program Latency ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays XC5200 Program Readback Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are ...
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Product Obsolete or Under Obsolescence R XC5200 Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from ...
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... IO XC5204 6.4 4.1 XC5206 6.6 4.2 XC5210 6.6 4.2 XC5215 7.3 4.6 T XC5202 7.8 5.6 ON XC5204 8.3 5.9 XC5206 8.4 6.0 XC5210 8.4 6.0 XC5215 8.9 6.3 T XC52xx 3.0 2.8 OFF November 5, 1998 (Version 5. Max Max (ns) (ns) 8.0 6.9 8 ...
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Product Obsolete or Under Obsolescence R XC5200 CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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... XC5204 IOB (Max) XC5206 . . . XC5210 . XC5215 T XC5202 PSUF XC5204 (Min) XC5206 XC5210 XC5215 T XC5202 PHF XC5204 (Min) XC5206 XC5210 XC5215 T XC5202 PSU XC5204 XC5206 XC5210 XC5215 T XC5202 L PSU XC5204 (Min) XC5206 XC5210 XC5215 T XC52xx PH (Min Max Max Max Max (ns) (ns) (ns) (ns) 16 ...
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Product Obsolete or Under Obsolescence R XC5200 IOB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all ...
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Product Obsolete or Under Obsolescence R Device-Specific Pinout Tables Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die, and include boundary scan register locations. Pin Locations for XC5202 Devices The following table ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description VQ64* 35. I/O (HDC) 19 36. I/O - 37. I/O (LDC) 20 GND - 38. I/O - 39. I/O 21 40. I/O - 41. I/O - 42. ...
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Product Obsolete or Under Obsolescence R Pin Description VQ64* CCLK 48 VCC - 74. I/O (TDO) 49 GND - 75. I/O (A0, WS) 50 76. GCK4 (A1, I/O) 51 77. I/O (A2, CS1) 52 78. I/O (A3) - GND - ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description 14. I/O 15. I/O (A14) 16. I/O (A15) VCC GND 17. GCK1 (A16, I/O) 18. I/O (A17) 19. I/O 20. I/O 21. I/O (TDI) 22. I/O (TCK) ...
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Product Obsolete or Under Obsolescence R Pin Description 57. I/O 58. I/O 59. I/O 60. I/O 61. I/O 62. I/O 63. I/O (ERR, INIT) VCC GND 64. I/O 65. I/O 66. I/O 67. I/O 68. I/O 69. I/O 70. I/O ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description 99. I/O 100. I/O 101. I/O GND 102. I/O (D1) 103. I/O (RCLK-BUSY/RDY) 104. I/O 105. I/O 106. I/O (D0, DIN) 107. I/O (DOUT) CCLK VCC 108. ...
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... Product Obsolete or Under Obsolescence R Pin Locations for XC5206 Devices The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC5200 Series data sheet for availability information. Pin Description PC84 PQ100 VCC I/O (A8) ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description PC84 PQ100 42. I/O - 43. I/O 25 44. I/O 26 45. I/O - 46. I/O - GND - 47. I/O - 48. I/O - 49. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PC84 PQ100 87. I/O - 88. I 89. I 90. I/O - 91. I/O - 92. I 93. I GND 52 52 DONE 53 ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description PC84 PQ100 CCLK 73 VCC 74 130. I/O (TDO) 75 GND 76 131. I/O (A0, WS) 77 132. GCK4 (A1, I/O) 78 133. I/O - 134. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PC84 7. I/O (A10) 8. I/O (A11) VCC 9. I/O 10. I/O 11. I/O 12. I/O GND 13. I/O 14. I/O 15. I/O 16. I/O 17. I/O (A12) 18. I/O (A13) 19. ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description PC84 50. I/O 51. I/O 52. I/O 53. I/O 54. I/O 55. I/O 56. I/O VCC 57. I/O 58. I/O 59. I/O 60. I/O GND 61. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PC84 95. I/O 96. I/O 97. I/O 98. I/O 40 99. I/O (ERR, INIT) 41 VCC 42 GND 43 100. I/O 44 101. I/O 45 102. I/O 103. I/O 104. I/O 105. ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description PC84 137. I/O 138. I/O 139. I/O VCC 140. I/O (D5) 141. I/O (CS0) 142. I/O 143. I/O 144. I/O 145. I/O 146. I/O (D4) 147. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PC84 180. I/O 181. I/O 182. I/O 183. I/O 184. I/O - GND 185. I/O 186. I/O 187. I/O 188. I/O VCC 189. I/O (A4) 81 190. I/O (A5) 82 191. I/O ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description 8. I/O (A11) 9. I/O 10. I/O VCC 11. I/O 12. I/O 13. I/O 14. I/O GND 15. I/O 16. I/O 17. I/O 18. I/O 19. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PQ160 54. I/O 55. I/O 56. I/O 57. I/O 58. I/O 59. I/O 60. I/O GND VCC 61. I/O 62. I/O 63. I/O 64. I/O 65. I/O 66. I/O 67. I/O 68. ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description 100. I/O 101. I/O 102. I/O 103. I/O 104. I/O 105. I/O 106. I/O 107. I/O 108. I/O 109. I/O GND 110. I/O 111. I/O 112. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PQ160 146. I/O 147. I/O 148. I/O 149. I/O 150. I/O 151. I/O 152. I/O 153. I/O GND DONE VCC PROG 154. I/O (D7) 155. GCK3 (I/O) 156. I/O 157. I/O 158. ...
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Product Obsolete or Under Obsolescence XC5200 Series Field Programmable Gate Arrays Pin Description 190. I/O 191. I/O 192. I/O (D2) 193. I/O VCC 194. I/O 195. I/O 196. I/O 197. I/O GND 198. I/O 199. I/O 200. I/O 201. I/O ...
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Product Obsolete or Under Obsolescence R Pin Description PQ160 235. I/O 236. I/O 237. I/O (A4) 238. I/O (A5) 239. I/O 240. I/O 241. I/O 242. I/O 243. I/O (A6) 244. I/O (A7) GND Additional No Connect (N.C.) Connections for ...
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... VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only. User I/O Per Package Max Device I/O VQ64 PC84 PQ100 XC5202 XC5204 124 65 81 XC5206 148 65 81 XC5210 196 65 XC5215 244 7/8/98 Ordering Information Example: Device Type Speed Grade 7-154 100 144 ...
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Product Obsolete or Under Obsolescence R Revisions Version 12/97 Rev 5.0 added -3, -4 specification 7/98 Rev 5.1 added Spartan family to comparison, removed HQ304 11/98 Rev 5.2 All specifications made final. November 5, 1998 (Version 5.2) XC5200 Series Field ...
XC5206-5TQ144C
XC5204-3PQ160C
XC5206-5PQ208C
XC5204-6VQ100C
XC5206-5PQ160C