XC5202-5PQ100C Xilinx Inc, XC5202-5PQ100C Datasheet - Page 24

• Manufacturer Part Number: XC5202-5PQ100C
• Description: IC - FPGA SPEED GRADE 5 COM TEMP
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-5PQ100C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 81
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Case: QFP100
• Dc: 01+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: Q858790; XC5202-5PQ1000C; XC5202-5PQ1000C

XC5200 Series Field Programmable Gate Arrays
Express Mode
Express mode is similar to Slave Serial mode, except the
data is presented in parallel format, and is clocked into the
target device a byte at a time rather than a bit at a time. The
data is loaded in parallel into eight different columns: it is
not internally serialized. Eight bits of configuration data are
loaded with every CCLK cycle, therefore this configuration
mode runs at eight times the data rate of the other six
modes. In this mode the XC5200 family is capable of sup-
porting a CCLK frequency of 10 MHz, which is equivalent to
an 80 MHz serial rate, because eight bits of configuration
data are being loaded per CCLK cycle. An XC5210 in the
Express mode, for instance, can be configured in about 2
ms. The Express mode does not support CRC error check-
ing, but does support constant-field error checking. A
length count is not used in Express mode.
In the Express configuration mode, an external signal
drives the CCLK input(s). The first byte of parallel configu-
ration data must be available at the D inputs of the FPGA
devices a short set-up time before the second rising CCLK
edge. Subsequent data bytes are clocked in on each con-
secutive rising CCLK edge. See
Bitstream generation currently generates a bitstream suffi-
cient to program in all configuration modes except Express.
Extra CCLK cycles are necessary to complete the configu-
ration, since in this mode data is read at a rate of eight bits
per CCLK cycle instead of one bit per cycle. Normally the
entire start-up sequence requires a number of bits that is
equal to the number of CCLK cycles needed. An additional
five CCLKs (equivalent to 40 extra bits) will guarantee com-
pletion of configuration, regardless of the start-up options
chosen.
Multiple slave devices with identical configurations can be
wired with parallel D0-D7 inputs.
devices can be configured simultaneously.
7-106
Figure 22: CCLK Generation for XC3000 Master
Driving an XC5200-Series Slave
0
1
1
0
0
Reset
.
.
etc
0
0
1
1
1
.
.
Active Low Output
Active High Output
Product Obsolete or Under Obsolescence
Figure 38 on page
In this way, multiple
OE/T
Output
Connected
to CCLK
123.
X5223
Pseudo Daisy Chain
Multiple devices with different configurations can be con-
nected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bit-
stream is used to configure the chain of Express mode
devices, but the input data bus must drive D0-D7 of each
device. Tie High the CS1 pin of the first device to be config-
ured, or leave it floating in the XC5200 since it has an inter-
nal pull-up. Connect the DOUT pin of each FPGA to the
CS1 pin of the next device in the chain. The D0-D7 inputs
are wired to each device in parallel. The DONE pins are
wired together, with one or more internal DONE pull-ups
activated. Alternatively, a 4.7 k
used, if desired. (See
are tied together.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All devices in Express mode are synchronized to the DONE
pin. User I/O for each device become active after the
DONE pin for that device goes High. (The exact timing is
determined by options to the bitstream generation soft-
ware.) Since the DONE pin is open-drain and does not
drive a High value, tying the DONE pins of all devices
together prevents all devices in the chain from going High
until the last device in the chain has completed its configu-
ration cycle.
The status pin DOUT is pulled LOW two internal-oscillator
cycles (nominally 1 MHz) after INIT is recognized as High,
and remains Low until the device’s configuration memory is
full. Then DOUT is pulled High to signal the next device in
the chain to accept the configuration data on the D7-D0
bus. All devices receive and recognize the six bytes of pre-
amble and length count, irrespective of the level on CS1;
but subsequent frame data is accepted only when CS1 is
High and the device’s configuration memory is not already
full.
Setting CCLK Frequency
For Master modes, CCLK can be generated in one of three
frequencies. In the default slow mode, the frequency is
nominally 1 MHz. In fast CCLK mode, the frequency is
nominally 12 MHz. In medium CCLK mode, the frequency
is nominally 6 MHz. The frequency range is -50% to +50%.
The frequency is selected by an option when running the
bitstream generation software. If an XC5200-Series Master
is driving an XC3000- or XC2000-family slave, slow CCLK
mode must be used. Slow mode is the default.
Table 11: XC5200 Bitstream Format
Fill Byte
Preamble
Length Counter
Fill Byte
Data Type
Figure 37 on page
November 5, 1998 (Version 5.2)
11111111
11111111
11110010
COUNT(23:0)
Value
external resistor can be
122.) CCLK pins
Once per bit-
stream
Occurrences
R