XC4013XL-1PQ208I Xilinx Inc, XC4013XL-1PQ208I Datasheet - Page 8

• Manufacturer Part Number: XC4013XL-1PQ208I
• Description: IC FPGA I-TEMP 3.3V 1SPD 208PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4013XL-1PQ208I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 160
• Number Of Gates: 13000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Output Flip-Flop, Clock to Out
Capacitive Load Factor
Figure 60
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 60
of voltage and temperature and is independent of the out-
put slew rate control.
6-80
Global Low Skew Clock to Output us-
ing Output Flip Flop
For output SLOW option add
Notes: Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
Output timing is measured at ~50% V
shows the relationship between I/O output delay
is usable over the specified operating conditions
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Description
T
Symbol
CC
T
ICKOF
SLOW
threshold with 50 pF external capacitive load. For different loads, see Figure 60.
Speed Grade
All Devices
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
Device
Figure 60: Delay Factor at Various Capacitive Loads
Min
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.1
2.2
2.3
2.5
0.5
All
DS005 (v. 1.8 October 18, 1999 - Product Specification
-1
-2
3
2
1
0
0
Max
10.3
10.7
11.3
12.2
7.1
7.7
8.2
8.6
9.0
9.4
9.8
3.0
-3
20
Max
10.5
Capacitance (pF)
6.1
6.6
7.1
7.4
7.8
8.1
8.5
8.9
9.3
9.7
2.5
40
-2
60
Max
5.4
5.8
6.2
6.5
6.8
7.1
7.4
7.8
8.3
8.5
9.5
2.0
-1
80
Max
All devices are 100%
-09
5.1
5.4
5.8
6.1
6.4
6.7
7.0
7.4
7.9
8.1
9.0
1.7
100 120 140
Max
-08
5.6
6.4
7.3
1.6
Units
X8257
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R