XCS10XL-4CS144C Xilinx Inc, XCS10XL-4CS144C Datasheet - Page 53

• Manufacturer Part Number: XCS10XL-4CS144C
• Description: IC FPGA 3.3V C-TEMP 144-CSA
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS10XL-4CS144C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-TFBGA, CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan-XL Family DC Characteristics Over Operating Conditions
Supply Current Requirements During Power-On
Spartan-XL FPGAs require that a minimum supply current
I
on. If more current is available, the FPGA can consume
more than I
reliability.
DS060 (v1.8) June 26, 2008
Product Specification
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
CCPO
Symbol
Symbol
I
T
I
I
CCPD
I
I
V
V
V
With up to 64 pins simultaneously sinking 12 mA (default mode).
With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected).
With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option.
With no output current loads, no active input resistors, and all package pins at V
With PWRDWN active.
The I
The ramp time is measured from GND to V
V
CCO
C
CCPO
RPU
RPD
CCPO
I
OH
DR
OL
CC
L
IN
be provided to the V
must not dip in the negative direction during power on.
CCPO
CCPO
R
High-level output voltage @ I
High-level output voltage @ I
Low-level output voltage @ I
Low-level output voltage @ I
Low-level output voltage @ I
Data retention supply voltage (below which configuration data
may be lost)
Quiescent FPGA supply current
Power Down FPGA supply current
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
Pad pull-down (when selected) @ V
requirement applies for a brief time (commonly only a few milliseconds) when V
Total V
V
CC
min., though this cannot adversely affect
ramp time
CC
supply current required during power-on
CC
(2,3)
lines for a successful power
Description
Description
OL
OL
OL
OH
OH
CC
= 12.0 mA, V
= 24.0 mA, V
= 1500 μA, (LVCMOS)
(3,4)
= –4.0 mA, V
= –500 μA, (LVCMOS)
max on a fully loaded board.
IN
(3,5)
= 0V (sample tested)
IN
= 3.3V (sample tested)
www.xilinx.com
CC
CC
CC
min (LVTTL)
min (LVTTL)
min (LVTTL)
A maximum limit for I
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of I
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
Commercial
Industrial
Commercial
Industrial
Spartan and Spartan-XL FPGA Families Data Sheet
(1)
(2)
CC
or GND.
90% V
0.02
0.02
Min
–10
CCPO
2.4
2.5
-
-
-
-
-
-
-
-
CC
Min
100
CC
CCPO
-
ramps from 0 to 3.3V.
is not specified. Be careful when
by limiting the supply current
Typ.
0.1
0.1
0.1
0.1
-
-
-
-
-
-
-
-
-
-
Max
50
-
10% V
Max
0.25
0.4
0.4
2.5
2.5
10
10
5
5
-
-
-
-
CC
Units
mA
ms
Units
mA
mA
mA
mA
mA
mA
μA
pF
V
V
V
V
V
V
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