CY7C63723C-SXC Cypress Semiconductor Corp, CY7C63723C-SXC Datasheet - Page 16

• Manufacturer Part Number: CY7C63723C-SXC
• Description: IC MCU 8K LS USB/PS-2 18-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63723C-SXC

• Package / Case: 18-SOIC (7.5mm Width)
• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 10
• Voltage - Supply: 3.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Product: USB and PS/2 Controller
• Number Of I/os: 10
• Operating Supply Voltage: 11 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 300 mW
• Number Of Timers: 4
• Core Size: 8 Bit
• No. Of I/o's: 10
• Program Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Embedded Interface Type: PS/2, USB
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1855

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Note that open drain mode can be achieved by fixing the Data
and Mode1 Registers LOW, and switching the Mode0 register.
Input thresholds are CMOS, or TTL as shown in the table (See
Section for the input threshold voltage in TTL or CMOS modes).
Both input modes include hysteresis to minimize noise sensi-
tivity. In suspend mode, if a pin is used for a wake-up interrupt
using an external R-C circuit, CMOS mode is preferred for lowest
power.
Table 3. Ports 0 and 1 Output Control Truth Table
Auxiliary Input Port
Port 2 serves as an auxiliary input port as shown in Figure . The
Port 2 inputs all have TTL input thresholds.
Figure 13. Port 2 Data Register (Address 0x02)
Document #: 38-08022 Rev. *D
Name
Read/
Reset
Write
Bit #
High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data
Register = 0)
High Drive Mode (Mode1 = 0 or 1, Mode0 = 1, and the pin’s
Data Register = 1)
Resistive Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Register = 1)
Bit
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 50 mA of current.
Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is capable of
sourcing 2 mA of current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14-kΩ resistor.
Register
Data
0
1
0
1
0
1
0
1
Reserved
7
0
-
6
0
-
Mode1 Mode0
(SCLK)
0
0
1
1
State
D+
R
5
0
(SDATA)
0
1
0
1
State
D–
R
4
0
Output Drive
High (50 mA)
(8 mA) Sink
Low (2 mA)
High Drive
High Drive
Reserved
Strength
Resistive
Medium
3
0
-
Hi-Z
Hi-Z
Sink
Sink
2
0
-
(Internal
Clock
Mode
Only)
P2.1
Threshold
R
1
0
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Input
TTL
VREG
State
P2.0
Pin
R
0
0
Bit [7:6]: Reserved
Bit [5:4]: D+ (SCLK) and D– (SDATA) States
Bit [3:2]: Reserved
Bit 1: P2.1 (Internal Clock Mode Only)
Bit 0: P2.0/VREG Pin State
USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB
host. The SIE simplifies the interface between the microcon-
troller and USB by incorporating hardware that handles the
following USB bus activity independently of the microcontroller:
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Firmware is required to handle the rest of the USB interface with
the following tasks:
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Translate the encoded received data and format the data to be
transmitted on the bus.
CRC checking and generation. Flag the microcontroller if errors
exist during transmission.
Address checking. Ignore the transactions not addressed to
the device.
Send appropriate ACK/NAK/STALL handshakes.
Token type identification (SETUP, IN, or OUT). Set the appro-
priate token bit once a valid token is received.
Place valid received data in the appropriate endpoint FIFOs.
Send and update the data toggle bit (Data1/0).
Bit stuffing/unstuffing.
Coordinate enumeration by decoding USB device requests.
Fill and empty the FIFOs.
Suspend/Resume coordination.
Verify and select Data toggle values.
The state of the D+ and D– pins can be read at Port 2 Data
Register. Performing a read from the port pins returns their
logic values.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
In the Internal Clock mode, the XTALIN pin can serve as a
general purpose input, and its state can be read at Port 2, Bit
1 (P2.1). See Section for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
In PS/2 mode, the VREG pin can be used as an input and its
state can be read at port P2.0. Section for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
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