CY7C66013C-PVXC Cypress Semiconductor Corp, CY7C66013C-PVXC Datasheet - Page 26

• Manufacturer Part Number: CY7C66013C-PVXC
• Description: IC MCU 8K USB HUB 4 PORT 48-SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013C-PVXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 29
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Controller Family/series: (8051) USB
• No. Of I/o's: 29
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C66xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2261-5; CY7C66013C-PVXC

Processor Status and Control Register
Processor Status and Control
Bit 0: Run
This bit is manipulated by the HALT instruction. When Halt is
executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the
processor stops at the end of the current instruction. The
processor remains halted until an appropriate reset occurs
(power on or Watchdog). This bit should normally be written as
a ‘1.’
Bit 1: Reserved
Bit 1 is reserved and must be written as a zero.
Bit 2: Interrupt Enable Sense
This bit indicates whether interrupts are enabled or disabled.
Firmware has no direct control over this bit as writing a zero or
one to this bit position has no effect on interrupts. A ‘0’ indicates
that interrupts are masked off and a ‘1’ indicates that the
interrupts are enabled. This bit is further gated with the bit
settings of the Global Interrupt Enable Register
USB End Point Interrupt Enable Register
Instructions DI, EI, and RETI manipulate the state of this bit.
Bit 3: Suspend
Writing a ‘1’ to the Suspend bit halts the processor and cause the
microcontroller to enter the suspend mode that significantly
reduces power consumption. A pending, enabled interrupt or
USB bus activity causes the device to come out of suspend. After
coming out of suspend, the device resumes firmware execution
at the instruction following the IOWR which put the part into
suspend. An IOWR attempting to put the part into suspend is
ignored if USB bus activity is present. See
page 15 for more details on suspend mode operation.
Bit 4: Power on Reset
The POR is set to ‘1’ during a power on reset. The firmware
checks bits 4 and 6 in the reset handler to determine whether a
reset was caused by a power on condition or a Watchdog
timeout. A POR event may be followed by a WDR before
firmware begins executing, as explained here.
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
7
IRQ
Pending
R
0
6
Reset
R/W
0
Watchdog
Figure 28. Processor Status and Control Register
5
USB Bus
Reset
Interrupt
R/W
0
Suspend Mode
(Figure
(Figure
29) and
4
Power On
Reset
R/W
1
30).
on
Bit 5: USB Bus Reset Interrupt
The USB Bus Reset Interrupt bit is set when the USB Bus Reset
is detected on receiving a USB Bus Reset signal on the upstream
port. The USB Bus Reset signal is a single ended zero (SE0) that
lasts from 12 to 16 μs. An SE0 is defined as the condition in which
both the D+ line and the D– line are LOW at the same time.
Bit 6: WDR
The WDR is set during a reset initiated by the WDT. This
indicates the WDT went for more than t
between Watchdog clears. This occurs with a POR event.
Bit 7: IRQ Pending
The IRQ pending, when set, indicates that one or more of the
interrupts is recognized as active. An interrupt remains pending
until its interrupt enable bit is set
interrupts are globally enabled. At that point, the internal interrupt
handling sequence clears this bit until another interrupt is
detected as pending.
During power up, the Processor Status and Control Register is
set to 00010001, which indicates a POR (bit 4 set) has occurred
and no interrupts are pending (bit 7 clear). During the 96 ms
suspend at start up (explained in
a WDR also occurs unless this suspend is aborted by an
upstream SE0 before 8 ms. If a WDR occurs during the power
up suspend interval, firmware reads 01010001 from the Status
and Control Register after power up. Normally, the POR bit
should be cleared so a subsequent WDR is clearly identified. If
an upstream bus reset is received before firmware examines this
register, the Bus Reset bit may also be set.
During a WDR, the Processor Status and Control Register is set
to 01XX0001, which indicates a WDR (bit 6 set) has occurred
and no interrupts are pending (bit 7 clear). The WDR does not
effect the state of the POR and the Bus Reset Interrupt bits.
3
R/W
0
Suspend
CY7C66013C, CY7C66113C
2
Interrupt
Enable
Sense
R
0
Power on Reset
1
R/W
0
Reserved
(Figure
WATCH
29,
ADDRESS 0xFF
(8 ms minimum)
Figure
0
Run
R/W
1
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