CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 34

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Hub Downstream Ports Status and Control
Data transfer on hub downstream ports is controlled according
to the bit settings of the Hub Downstream Ports Control Register
(Figure
defined in
Register is cleared upon reset or bus reset, and the reset state
is the state for normal USB traffic. Any downstream port being
forced must be marked as disabled
operation of the hub repeater.
Firmware uses this register for driving bus reset and resume
signaling to downstream ports. Controlling the port pins through
Hub Downstream Ports Control Register
Table 12. Control Bit Definition for Downstream Ports
An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register
the pins of the downstream ports are individually forced LOW, or left unforced. Unlike the Hub Downstream Ports Control Register,
above, the Force Low Register does not produce standard USB edge rate control on the forced pins. However, this register allows
downstream port pins to be held LOW in suspend. This register is used to drive SE0 on all downstream ports when unconfigured, as
required in the USB 1.1 specification.
Hub Ports Force Low
The data state of downstream ports are read through the HUB Ports SE0 Status Register
(Figure
Ports Speed Register
Data Register hold the last differential data state before the SE0. Hub Ports SE0 Status Register and Hub Ports Data Register are
cleared upon reset or bus reset.
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit1
39). The data read from the Hub Ports Data Register is the differential data only and is independent of the settings of the Hub
36). Each downstream port is controlled by two bits, as
0
0
1
1
Control Bits
Table
7
Force Low
D+[4]
R/W
0
7
Port 4
Control Bit 1
R/W
0
12. The Hub Downstream Ports Control
(Figure
Bit 0
0
1
0
1
6
Force Low
D-[4]
R/W
0
6
Port 4
Control Bit 0
R/W
0
34). When the SE0 condition is sensed on a downstream port, the corresponding bits of the Hub Ports
Not Forcing (Normal USB Function)
Force Differential ‘1’ (D+ HIGH, D– LOW)
Force Differential ‘0’ (D+ LOW, D– HIGH)
Force SE0 state
Figure 36. Hub Downstream Ports Control Register
(Figure
Figure 37. Hub Ports Force Low Register
5
Force Low
D+[3]
R/W
0
5
Port 3
Control Bit 1
R/W
0
35) for proper
4
Force Low
D–[3]
R/W
0
4
Port 3
Control Bit 0
R/W
0
this register uses standard USB edge rate control according to
the speed of the port, set in the Hub Port Speed Register.
The downstream USB ports are designed for connection of USB
devices, but also serves as output ports under firmware control.
This allows unused USB ports to be used for functions such as
driving LEDs or providing additional input signals. Pulling up
these pins to voltages above V
the pin.
This register is not reset by bus reset. These bits must be cleared
before going into suspend.
0
3
Force Low
D+[2]
R/W
3
Port 2
Control Bit 1
R/W
0
Control Action
CY7C66013C, CY7C66113C
(Figure
2
Force Low
D–[2]
R/W
0
2
Port 2
Control Bit 0
R/W
0
38) and the Hub Ports Data Register
(Figure
REF
1
Force Low
D+[1]
R/W
0
may cause current flow into
1
Port 1
Control Bit 1
R/W
0
37). With these registers
ADDRESS 0x4B
ADDRESS 0x51
0
Force Low
D–[1]
R/W
0
Page 34 of 59
0
Port 1
Control Bit 0
R/W
0
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