CY7C68013A-100AXC Cypress Semiconductor Corp, CY7C68013A-100AXC Datasheet - Page 44

• Manufacturer Part Number: CY7C68013A-100AXC
• Description: IC MCU USB PERIPH HI SPD 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-100AXC

• Program Memory Type: ROMless
• Package / Case: 100-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: 0 C
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Package: 100TQFP
• Family Name: FX2LP
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3 V
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1667

10.8 Slave FIFO Asynchronous Read
Table 22. Slave FIFO Asynchronous Read Parameters
Document #: 38-08032 Rev. *M
Note
t
t
t
t
t
t
RDpwl
RDpwh
XFLG
XFD
OEon
OEoff
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Parameter
SLRD Pulse Width LOW
SLRD Pulse Width HIGH
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
FLAGS
DATA
Figure 19. Slave FIFO Asynchronous Read Timing Diagram
SLOE
SLRD
Description
t
OEon
N
[23]
t
RDpwl
t
XFD
N+1
t
XFLG
t
t
RDpwh
OEoff
Min
50
50
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[20]
Max
10.5
10.5
15
70
Page 44 of 62
Unit
ns
ns
ns
ns
ns
ns
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