CY7C67300-100AXI Cypress Semiconductor Corp, CY7C67300-100AXI Datasheet - Page 66

• Manufacturer Part Number: CY7C67300-100AXI
• Description: IC USB HOST/PERIPH CNTRL 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-Host™r
• Type: Host Programmable Embedded USBr

Specifications of CY7C67300-100AXI

• Package / Case: 100-LQFP
• Applications: USB Host/Peripheral Controller
• Core Processor: CY16
• Program Memory Type: ROM (8 kB)
• Controller Series: CY7C673xx
• Ram Size: 16K x 8
• Interface: SPI Serial, USB, HPI
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 80 mA
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4640 - KIT MASS STORAGE REF DESIGNCY3663 - KIT DEV EZ-OTG/EZ-HOST
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1865; CY7C67300-100AXI

SPI Configuration Register [0xC0C8] [R/W]
Table 105. SPI Configuration Register
Register Description
The SPI Configuration register controls the SPI port. Fields apply
to both master and slave mode unless otherwise noted.
3Wire Enable (Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data lines
are tied together allowing only half duplex operation.
1: MISO and MOSI data lines are tied together
0: Normal MISO and MOSI Full Duplex operation (not tied
together)
Phase Select (Bit 14)
The Phase Select bit selects advanced or delayed SCK phase.
This field only applies to master mode.
1: Advanced SCK phase
0: Delayed SCK phase
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.
1: Positive SCK polarity
0: Negative SCK polarity
Scale Select (Bits [12:9])
The Scale Select field provides control over the SCK frequency,
based on 48 MHz. Refer to
This field only applies to master mode.
Table 106. Scale Select Field Definition for SCK Frequency
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
Scale Select [12:9]
0000
0001
0010
0011
0100
0101
0110
1000
0111
Enable
Master
Enable
Active
3Wire
R/W
15
R
1
7
0
Table 106
Master
Enable
Phase
Select
R/W
R/W
14
0
6
0
SCK Frequency
for a definition of this field.
750 KHz
1.5 MHz
12 MHz
8 MHz
6 MHz
4 MHz
3 MHz
2 MHz
1 MHz
SCK Polarity
Enable
Select
R/W
R/W
SS
13
0
5
0
R/W
R/W
12
0
4
1
Table 106. Scale Select Field Definition for SCK Frequency
Master Active Enable (Bit 7)
The Master Active Enable bit is a read only bit that indicates if
the master state machine is active or idle. This field only applies
to master mode.
1: Master state machine is active
0: Master state machine is idle
Master Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or slave.
This bit is only writable when the Master Active Enable bit reads
‘0’, otherwise the value does not change.
1: Master SPI interface
0: Slave SPI interface
SS Enable (Bit 5)
The SS Enable bit enables or disables the master SS output.
1: Enable master SS output
0: Disable master SS output (three state master SS output, for
single SS line in slave mode)
SS Delay Select (Bits [4:0])
When the SS Delay Select field is set to ‘00000’ this indicates
manual mode. In manual mode SS is controlled by the SS
Manual bit of the SPI Control register. When the SS Delay Select
field is set between ‘00001’ to ‘11111’, this value indicates the
count in half bit times of auto transfer delay for: SS low to SCK
active, SCK inactive to SS high, SS high time. This field only
applies to master mode.
Scale Select [12:9]
R/W
R/W
11
3
1
0
Scale Select
1001
1010
1011
1100
1101
1110
1111
SS Delay Select
R/W
R/W
10
2
1
0
R/W
R/W
SCK Frequency
1
1
9
0
500 KHz
375 KHz
375 KHz
250 KHz
250 KHz
375 KHz
250 KHz
CY7C67300
Reserved
Page 66 of 99
R/W
0
1
8
0
-
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