CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet
CY7C68013A-128AXI
Specifications of CY7C68013A-128AXI
CY7C68013A-128AXI
Available stocks
Related parts for CY7C68013A-128AXI
CY7C68013A-128AXI Summary of contents
Page 1
... CY7C68015A: Ideal for Non Battery Powered Applications ■ Suspend current: 300 A (typ) ❐ Available in Pb-free 56-pin QFN Package (26 GPIOs) ■ Two more GPIOs than CY7C68013A/14A enabling additional ■ features in same footprint • 198 Champion Court • San Jose CY7C68013A, CY7C68014A ...
Page 2
... Enhanced USB core Simplifies 8051 code ® Cypress’s EZ-USB FX2LP (CY7C68013A/14A low power version of the EZ-USB FX2(CY7C68013), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral ...
Page 3
... GPIF .......................................................................... 13 [7] ................................................................... 13 ECC Generation USB Uploads and Downloads ................................... 13 Autopointer Access ................................................... Controller ............................................................. 14 Compatible with Previous Generation EZ-USB FX2 . 14 CY7C68013A/14A and CY7C68015A/16A Differences 14 Pin Assignments ............................................................ 15 CY7C68013A/15A Pin Descriptions .......................... 22 Register Summary .......................................................... 30 Absolute Maximum Ratings .......................................... 37 Operating Conditions ..................................................... 37 Thermal Characteristics ................................................. 37 DC Characteristics ......................................................... 38 USB Transceiver ....................................................... 38 AC Electrical Characteristics ........................................ 39 USB Transceiver ...
Page 4
... MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically. Note 1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively. Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 2-1. Crystal Configuration 24 MHz C1 ...
Page 5
... USB interrupt source, the FX2LP provides a second level of interrupt vectoring, called Autovectoring. When a USB interrupt is asserted, the FX2LP pushes the program counter to its stack, and then jumps to the address 0x0043 where it expects to find a “jump” instruction to the USB Interrupt service routine. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
Page 6
... Bus errors exceeded the programmed limit – Reserved Reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes Table 2-4 on page 7 shows the Page [+] Feedback ...
Page 7
... RESET# pin is asserted. Cypress provides an application note which describes and recommends power on reset implementation. For more information about reset implementation for the FX2 family of products visit http://www.cypress.com. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Notes [3] shows a power on reset condition and a ...
Page 8
... Setup data pointer ■ interface boot load. ■ 2.10.3 External Code Memory The bottom 16 KBytes of program memory is external and therefore the bottom 16 KBytes of internal RAM is accessible only as a data memory. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A RESET Powered Reset shows the Internal Code Memory shows the External Code Memory ...
Page 9
... External 40 KBytes Code External Memory Data (PSEN#) Memory (RD#,WR#) (Ok to populate (OK to populate data memory program here—RD#/WR# memory here— strobes are not PSEN# strobe active) is not active) Data Code 2 C interface boot access CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...
Page 10
... Bytes EP0 IN/OUT E740 E73F 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) E500 E4FF Reserved (128) E480 E47F 128 bytes GPIF Waveforms E400 E3FF Reserved (512) E200 E1FF 512 bytes 8051 xdata RAM E000 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...
Page 11
... EP6 EP6 EP6 EP6 EP6 512 512 512 1024 1024 512 512 512 EP8 EP8 512 512 512 1024 1024 512 512 512 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EP2 EP2 EP2 EP2 EP2 512 1024 1024 1024 512 1024 512 EP6 ...
Page 12
... FIFO. The slave interface can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
Page 13
... GPIF The GPIF is a flexible 8-bit or 16-bit parallel interface driven by a user programmable finite state machine. It enables the CY7C68013A/15A to perform local bus mastering and can implement a wide variety of protocols such as ATA interface, printer parallel port, and Utopia. The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs (RDY) ...
Page 14
... CY7C68013A/14A and CY7C68015A/16A 0 1 Differences CY7C68013A is identical to CY7C68014A in form, fit, and functionality. CY7C68015A is identical to CY7C68016A in form, fit, and functionality. CY7C68014A and CY7C68016A have a lower suspend current than CY7C68013A and CY7C68015A respectively and are ideal for power sensitive battery applications. ...
Page 15
... The signals on the left edge of the 56-pin package in on page 16 are common to all versions in the FX2LP family with the noted differences between the CY7C68013A/14A and the CY7C68015A/16A. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram ...
Page 16
... PORTC2/GPIFADR2 PORTC1/GPIFADR1 PORTC0/GPIFADR0 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 3-1. Signal Port GPIF Master PD7 FD[15] PD6 FD[14] FD[13] PD5 PD4 FD[12] PD3 FD[11] FD[10] PD2 PD1 FD[9] PD0 FD[8] PB7 ...
Page 17
... Figure 3-2. CY7C68013A/CY7C68014A 128-Pin TQFP Pin Assignment CLKOUT 1 VCC 2 GND 3 RDY0/*SLRD 4 RDY1/*SLWR 5 RDY2 6 RDY3 7 RDY4 8 RDY5 9 AVCC 10 XTALOUT 11 XTALIN 12 AGND AVCC 17 DPLUS 18 DMINUS 19 AGND 20 A11 21 A12 22 A13 23 A14 24 A15 25 VCC 26 GND 27 INT4 *IFCLK 32 RESERVED 33 BKPT SCL 36 SDA 37 OE# 38 Document #: 38-08032 Rev. *T ...
Page 18
... Figure 3-3. CY7C68013A/CY7C68014A 100-Pin TQFP Pin Assignment VCC 1 GND 2 RDY0/*SLRD 3 RDY1/*SLWR 4 RDY2 5 RDY3 6 RDY4 7 RDY5 8 AVCC 9 XTALOUT 10 XTALIN 11 AGND AVCC 16 DPLUS 17 DMINUS 18 AGND 19 VCC 20 GND 21 INT4 *IFCLK 26 RESERVED 27 BKPT 28 SCL 29 SDA 30 Document #: 38-08032 Rev. *T PA7/*FLAGD/SLCS# CY7C68013A/CY7C68014A 100-pin TQFP ...
Page 19
... Figure 3-4. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment Document #: 38-08032 Rev. *T CY7C68013A/CY7C68014A 56-pin SSOP PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 GND PD1/FD9 CLKOUT PD0/FD8 VCC *WAKEUP GND VCC RDY0/*SLRD RESET# RDY1/*SLWR GND AVCC PA7/*FLAGD/SLCS# XTALOUT PA6/PKTEND XTALIN PA5/FIFOADR1 AGND ...
Page 20
... Figure 3-5. CY7C68013A/14A/15A/16A 56-Pin QFN Pin Assignment RDY0/*SLRD 1 RDY1/*SLWR 2 AVCC 3 XTALOUT 4 XTALIN 5 AGND 6 AVCC 7 DPLUS 8 DMINUS 9 AGND 10 VCC 11 GND 12 *IFCLK/**PE0 13 RESERVED 14 Document #: 38-08032 Rev. *T CY7C68013A/CY7C68014A & CY7C68015A/CY7C68016A 56-pin QFN * denotes programmable polarity ** denotes CY7C68015A/CY7C68016A pinout CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A ...
Page 21
... Figure 3-6. CY7C68013A 56-pin VFBGA Pin Assignment – Top View Document #: 38-08032 Rev CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Page [+] Feedback ...
Page 22
... CY7C68013A/15A Pin Descriptions [10] The FX2LP pin descriptions follow. Table 3-1. FX2LP Pin Descriptions 128 100 TQFP TQFP SSOP QFN VFBGA AVCC AVCC AGND AGND DMINUS DPLUS 94 – – – – – – – – – – – – – – ...
Page 23
... I/O/Z I Multiplexed pin whose function is selected by two bits: (PA2) IFCONFIG[1:0]. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with program- mable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0]. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
Page 24
... PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus. I/O/Z I Multiplexed pin whose function is selected by the (PB4) following bits: IFCONFIG[1..0]. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
Page 25
... Multiplexed pin whose function is selected by the (PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. I/O/Z I Multiplexed pin whose function is selected by the (PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
Page 26
... PORTECFG.3 bit. PE3 is a bidirectional I/O port pin. RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when sync mode. Otherwise CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
Page 27
... RDY5 is a GPIF input signal. O/Z H Multiplexed pin whose function is selected by the following bits: IFCONFIG[1..0]. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
Page 28
... TXD1is an active-HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode. Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description Page [+] Feedback ...
Page 29
... N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. N/A N/A No Connect. This pin must be left open. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Description chip from suspending interface. Connect to VCC with a 2. peripheral is attached. C compatible interface. Connect to VCC ...
Page 30
... PL7 PL6 PL5 PL4 PL3 PL7 PL6 PL5 PL4 PL3 LINE15 LINE14 LINE13 LINE12 LINE11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default xxxxxxxx RW reserved reserved reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGC2 FLAGC1 FLAGC0 ...
Page 31
... EP6 EP4 0 0 EP8 EP6 EP4 EP8 EP6 EP4 EP2 EP1 EP8 EP6 EP4 EP2 EP1 0 EP0ACK HSGRANT URES SUSP CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default LINE2 LINE1 LINE0 00000000 R COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R ...
Page 32
... BC3 BC7/SKIP BC6 BC5 BC4 BC3 BC7/SKIP BC6 BC5 BC4 BC3 BC7/SKIP BC6 BC5 BC4 BC3 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN 0 0 GPIFWF GPIFDONE 00000000 RW 0 GPIFWF GPIFDONE 000000xx RW 0 ...
Page 33
... CTL0E1/ CTL0E0/ CTL3 CTL5 CTL4 HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE SLAVE RDYASYNC CTLTOGL SUSTAIN TC31 TC30 TC29 TC28 TC27 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default 0 BUSY STALL 10000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb 0 BUSY STALL 00000000 bbbbbbrb EMPTY 0 STALL 00101000 rrrrrrrb EMPTY ...
Page 34
... TCXRDY5 RDY5 RDY4 RDY3 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default TC18 TC17 TC16 00000000 RW TC10 TC9 TC8 00000000 RW TC2 TC1 TC0 00000001 RW 00000000 RW 0 FS1 FS0 00000000 FIFO2FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 FIFO4FLAG 00000000 xxxxxxxx W 0 FS1 FS0 00000000 FIFO6FLAG 00000000 RW ...
Page 35
... EP8FF PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default 0 0 400KHZ xxxxxxxx [14 xxxxxxxx 00000111 00000000 RW A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 SEL 00000000 IDLE 00110000 RW IT1 IE0 IT0 00000000 00000000 00000000 00000000 RW D10 D9 ...
Page 36
... TCLK EXEN2 D15 D14 D13 D12 D11 RS1 RS0 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Default xxxxxxxx xxxxxxxx R RB8_1 TI_1 RI_1 00000000 00000000 RW TR2 CT2 CPRL2 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 00000000 01000000 RW D2 ...
Page 37
... Case to Ambient Temperature Temperature (°C/W) (°C/W) 24.4 23.3 11.9 34.0 15.5 27.7 10.6 14.6 30.9 27.7 = P* P* c CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A parallel resonant Ja Junction to Ambient Temperature (°C/W) 47.7 45.9 43.2 25.2 58.6 + Page [+] Feedback ...
Page 38
... Reset time after valid power RESET Pin reset after powered on 8.1 USB Transceiver USB 2.0 compliant in full speed and high speed modes. Note 16. Measured at Max VCC, 25 °C. Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Conditions – – – – – – ...
Page 39
... DH t ACC1 data in Min Typ – 20.83 – 41.66 – 83.2 0 – 0 – 0 – – – – – 9.6 – 0 – CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Max Unit Notes – MHz – MHz – MHz 10.7 ns – – – 11.1 ns – – ...
Page 40
... ACC1 Min Typ – 20.83 – 41.66 – 83.2 – – – – – – – – – – 9.6 – 0 – CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A t DSU t DH data in Max Unit Notes – MHz – MHz – MHz 10.7 ns – – ...
Page 41
... When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on the stretch value. Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A t t ...
Page 42
... Following is the timing diagram of the read and write strobing function on accessing PORTC. Refer to 9.4 for details on propagation delay of RD# and WR# signals. t STBL DATA CAN BE UPDATED BY EXTERNAL LOGIC DATA MUST BE HELD FOR 3 CLK CYLCES t STBL CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Section 9.3 and Section t STBH t STBH Page ...
Page 43
... SGA t SRY t RYH valid t t SGD DAH t XCTL N N+1 t XGD Description Min 20.83 8.9 9.2 Description Min. 20.83 2.9 3.7 3.2 4.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [20, 21] Max Unit – ns – – ns – – ns – 7.5 ns – – 6.7 ns [21] Max. ...
Page 44
... Clock to FIFO data output propagation delay XFD Document #: 38-08032 Rev IFCLK t RDH t SRD t XFLG N N OEon XFD Description Min 20.83 18.7 Description Min 20.83 12.7 3.7 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t OEoff [21] Max Unit – ns – – ns – 10.5 ns – 10.5 ns – 9.5 ns – 11 ...
Page 45
... SLOE turn-off to FIFO data hold OEoff Note 23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document #: 38-08032 Rev RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 50 – – ns – – – 10.5 ns – 10.5 ...
Page 46
... XFLG Document #: 38-08032 Rev IFCLK t WRH t SWR SFD FDH t XFLG Description Min 20.83 10.4 9.2 Description Min 20.83 12.1 3.6 3.2 4.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Z [21] Max Unit – ns – – ns – – ns – 9.5 ns [21] Max Unit 200 ns – ...
Page 47
... XFLG Document #: 38-08032 Rev WRpwh t WRpwl t t FDH SFD t XFD Description Min t PEH t SPE t XFLG Description Min 20.83 14.6 Description Min 20.83 8.6 2.5 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] [23] Max Unit 50 – – – – ns – [20] [21] Max Unit – ns – – ...
Page 48
... SFD FDH SFD FDH FDH SFD X-2 X-1 X-3 t PEpwh t PEpwl t XFLG [23] Description Min CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 9-12 shows this scenario the [20] t FAH >= t WRH SFD FDH FDH SFD least one IFCLK cycle t SPE t PEH [20] ...
Page 49
... Clock to FIFOADR[1:0] hold time FAH Document #: 38-08032 Rev OEoff t OEon Description Min t XFLG t XFD N N+1 Description Min t t SFA FAH [21] Description Min 20.83 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] Max Unit 10.5 ns 10.5 ns [20] Max Unit – 10.7 ns – 14.3 ns [20] Max Unit 200 ns 25 – ...
Page 50
... XFLG t XFD N+1 N OEon OEoff t=4 T=1 IFCLK IFCLK IFCLK N+1 N+1 N+1 SLOE SLRD SLOE SLRD SLRD N+1 Not Driven N+1 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH Min Max Unit 10 – – ns [20] t FAH >= t RDH T XFD XFD N+4 N+2 ...
Page 51
... RDH t t SFA FAH t >= t T=0 WRH SWR T=2 t XFLG t t FDH SFD N+1 T=1 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A (measured from the rising edge of XFD [20] t FAH >= t WRH T=5 t XFLG SFD FDH FDH SFD N+3 ...
Page 52
... FIFO, SLWR is deasserted. The short 4 byte packet can be committed to the host by asserting the PKTEND signal. Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A There is no specific timing requirement that should be met for asserting PKTEND signal with regards to asserting the SLWR signal ...
Page 53
... Note In burst read mode, during SLOE is assertion, the data bus driven state and outputs the previous data. After SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH ...
Page 54
... It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse before the width. The FIFOADDR lines have to held constant during the SFD PKTEND assertion. from the deasserting CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A [20] t FAH t t WRpwl ...
Page 55
... QFN – Pb-free CY7C68016A-56LTXC 56 QFN - Pb-free CY7C68016A-56LTXCT 56 QFN - Pb-free Ideal for Non Battery Powered Applications CY7C68013A-128AXC 128 TQFP – Pb-free CY7C68013A-128AXI 128 TQFP – Pb-free (Industrial) CY7C68013A-100AXC 100 TQFP – Pb-free CY7C68013A-100AXI 100 TQFP – Pb-free (Industrial) CY7C68013A-56PVXC 56 SSOP – Pb-free CY7C68013A-56PVXI 56 SSOP – ...
Page 56
... Package Diagrams The FX2LP is available in five packages: 56-pin SSOP ■ 56-pin QFN ■ 100-pin TQFP ■ 128-pin TQFP ■ 56-ball VFBGA ■ Figure 11-1. 56-Pin Shrunk Small Outline Package O56 (51-85062) Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 51-85062 *D Page [+] Feedback ...
Page 57
... Figure 11-2. 56-Pin QFN 8 × Punch Version (001-12921) Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 001-12921 *A Page [+] Feedback ...
Page 58
... Figure 11-3. 56-Pin QFN 8 × Sawn Version (001-53450) Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 001-53450 *B Page [+] Feedback ...
Page 59
... Figure 11-4. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A100RA (51-85050) Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 51-85050 *D Page [+] Feedback ...
Page 60
... Figure 11-5. 128-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 (51-85101) Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 51-85101 *E Page [+] Feedback ...
Page 61
... Figure 11-6. 56-Pin VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901) Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 001-03901 *C Page [+] Feedback ...
Page 62
... USB connector. Note 25. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Bypass and flyback caps on VBus, near connector, are ■ recommended. DPLUS and DMINUS trace lengths should be kept to within ■ ...
Page 63
... Solder Mask Cu Fill Cu Fill 0.013” dia PCB Material This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane Figure 13-3. X-ray Image of the Assembly CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Figure 13-3 Page [+] Feedback ...
Page 64
... USB universal serial bus UTOPIA universal test and operations physical-layer interface VFBGA very fine ball grid array VID vendor identifier Document #: 38-08032 Rev. *T CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document Conventions Units of Measure Symbol Unit of Measure KHz kilohertz mA milliamperes Mbps megabits per second ...
Page 65
... Document History Page Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB Speed USB Peripheral Controller Document Number: 38-08032 Rev. ECN No. Orig. of Submission Change Date ** 124316 VCS 03/17/03 *A 128461 VCS 09/02/03 *B 130335 KKV 10/09/03 *C 131673 KKU 02/12/04 *D 230713 KKU See ECN *E 242398 TMD ...
Page 66
... Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB Speed USB Peripheral Controller Document Number: 38-08032 Rev. ECN No. Orig. of Submission Change Date *L 2064406 CMCC/ See ECN PYRS *M 2710327 DPT 05/22/2009 Added 56-Pin QFN ( mm) package diagram *N 2727334 ODC 07/01/09 *O 2756202 ODC 08/26/2009 Updated Ordering Information table and added note 24. ...
Page 67
... C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised February 5, 2011 CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A PSoC Solutions psoc.cypress.com/solutions ...