CY7C63413-PVC Cypress Semiconductor Corp, CY7C63413-PVC Datasheet - Page 17

• Manufacturer Part Number: CY7C63413-PVC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PVC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1319

In “Resistive” mode, a 7 Kohm pull-up resistor is conditionally enabled for all pins of a GPIO port. The resistor is enabled for any
pin that has been written as a “1.” The resistor is disabled on any pin that has been written as a “0”. An I/O pin will be driven high
through a 7 Kohm pull-up resistor when a “1” has been written to the pin. Or the output pin will be driven LOW, with the pull-up
disabled, when a “0” has been written to the pin. An I/O pin that has been written as a “1” can be used as an input pin with an
integrated 7 Kohm pull-up resistor. Resistive mode selects a negative (falling edge) interrupt polarity on all pins that have the
GPIO interrupt enabled.
A port configured in CMOS mode has interrupt generation disabled, yet the interrupt mask bits serve to control port direction. If
a port’s associated Interrupt Mask bits are cleared, those port bits are strictly outputs. If the Interrupt Mask bits are set then those
bits will be open drain inputs. As open drain inputs, if their data output values are ‘1’ those port pins will be CMOS inputs (HIGH
Z output).
In “Open Drain” mode the internal pull-up resistor and CMOS driver (HIGH) are both disabled. An I/O pin that has been written
as a “1” can be used as either a high-impedance input or a three-state output. An I/O pin that has been written as a “0” will drive
the output LOW. The interrupt polarity for an open drain GPIO port can be selected as either positive (rising edge) or negative
(falling edge).
During reset, all of the bits in the GPIO Configuration Register are written with “0”. This selects the default configuration: Open
Drain output, positive interrupt polarity for all GPIO ports.
10.0
Config Bit 1
Port Configuration bits
Port 3
7
DAC Port
11
10
10
01
00
Internal
Data Bus
Config Bit 0
Port 3
6
Interrupt
Enable
Interrupt
Polarity
Figure 9-10. GPIO Configuration Register 0x08h (write only)
Config Bit 1
Internal
Buffer
Port 2
DAC Write
DAC Read
5
Pin Interrupt Bit
Data
Out
Latch
Figure 10-1. Block Diagram of DAC Port
X
X
X
0
1
Config Bit 0
Isink
Register
Port 2
4
4 bits
17
Isink
DAC
Config Bit 1
to Interrupt
Controller
Port 1
3
CMOS Output
Driver Mode
V
CMOS Input
Open Drain
Open Drain
CC
Resistive
Q1
14 K
Config Bit 0
Port 1
2
ESD
DAC
I/O Pin
Config Bit 1
CY7C63411/12/13
CY7C63511/12/13
Port 0
Interrupt Polarity
1
+ (default)
disabled
disabled
-
-
Config Bit 0
Port 0
0