CY7C64713-56LFXC Cypress Semiconductor Corp, CY7C64713-56LFXC Datasheet - Page 37

• Manufacturer Part Number: CY7C64713-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1680; CY7C64713-56LFXC

Slave FIFO Synchronous Read
In the following figure, dashed lines indicate signals with programmable polarity.
The following table provides the Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK.
Table 16. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
The following table provides the Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK.
Table 17. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Document #: 38-08039 Rev. *F
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
Parameter
Parameter
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
IFCLK Period
SLRD to Clock Setup Time
Clock to SLRD Hold Time
SLOE Turn on to FIFO Data Valid
SLOE Turn off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
SLOE
FLAGS
DATA
SLRD
IFCLK
Figure 19. Slave FIFO Synchronous Read Timing Diagram
Description
Description
t
OEon
N
t
SRD
t
IFCLK
t
RDH
t
XFLG
t
XFD
N+1
20.83
20.83
18.7
12.7
Min
Min
3.7
0
t
OEoff
Max
10.5
10.5
Max
10.5
10.5
13.5
200
9.5
15
11
[16]
[16]
CY7C64713
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 37 of 55
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