CY7C63413-PC Cypress Semiconductor Corp, CY7C63413-PC Datasheet - Page 14

• Manufacturer Part Number: CY7C63413-PC
• Description: IC MCU 8K USB LS PERIPH 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1318

7.0
The XTAL
external oscillator can be connected to these pins to provide a reference frequency for the internal clock distribution and clock
doubler.
An external 6 MHz clock can be applied to the XTAL
pin is not permissible as the internal clock is effectively shorted to ground.
8.0
The USB Controller supports three types of resets. All registers are restored to their default states during a reset. The USB Device
Addresses are set to 0 and all interrupts are disabled. In addition, the Program Stack Pointer (PSP) and Data Stack Pointer (DSP)
are set to 0x00. For USB applications, the firmware should set the DSP below 0xE8h to avoid a memory conflict with RAM
dedicated to USB FIFOs. The assembly instructions to do this are shown below:
The three reset types are:
The occurrence of a reset is recorded in the Processor Status and Control Register located at I/O address 0xFF. Bits 4, 5, and 6
are used to record the occurrence of POR, USB Reset, and WDR respectively. The firmware can interrogate these bits to
determine the cause of a reset.
The microcontroller begins execution from ROM address 0x0000h after a POR or WDR reset. Although this looks like interrupt
vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto
program stack. That means the reset handler in firmware should initialize the hardware and begin executing the “main” loop of
code. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results.
8.1
Power-On Reset (POR) occurs every time the V
of approximately 1/2 full supply voltage. In addition to the normal reset initialization noted under “Reset,” bit 4 (PORS) of t he
Processor Status and Control Register is set to “1” to indicate to the firmware that a power on reset occurred. The POR event
forces the GPIO ports into input mode (high impedance), and the state of Port 3 bit 7 is used to control how the part will respond
after the POR releases.
If Port 3 bit 7 is high (pulled to V
manent power down/suspend mode, waiting for the USB IO to go to one of Bus Reset, K (resume) or SE0. If Port 3 bit 7 is still
high when the part comes out of suspend, then a 128 us timer starts, delaying CPU operation until the ceramic resonator has
stabilized.
If Port 3 bit 7 was low (pulled to V
continuing to run as reset.
Firmware should clear the POR Status (PORS) bit in register FFh before going into suspend as this status bit selects the 128 s
or 128 ms start-up timer value as follows: IF Port 3 bit 7 is high then 128 s is always used; ELSE if PORS is high then 128 ms
is used; ELSE 128 s is used.
1. Power-On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Bus Reset (non hardware reset)
Mov A, E8h
Swap A,dsp
Power-On Reset (POR)
Clocking
Reset
IN
and XTAL
; Move 0xE8 hex into Accumulator
; swap accumulator value into dsp register
Clock Distribution
OUT
(to Microcontroller)
(to USB SIE)
are the clock pins to the microcontroller. The user can connect a low-cost ceramic resonator or an
clk1x
clk2x
CC
SS
) and the USB IO are at the idle state (DM high and DP low) the part will go into a semi-per-
) the part will start a 128 ms timer, delaying CPU operation until V
Figure 7-1. Clock Oscillator On-chip Circuit
Doubler
CC
Clock
voltage to the device ramps from 0V to an internally defined trip voltage (Vrst),
IN
pin if the XTAL
30pF
14
OUT
pin is left open. Please note that grounding the XTAL
30pF
XTALOUT
XTALIN
CY7C63411/12/13
CY7C63511/12/13
CC
has stabilized, then
OUT