CY7C63413-PC Cypress Semiconductor Corp, CY7C63413-PC Datasheet - Page 29

• Manufacturer Part Number: CY7C63413-PC
• Description: IC MCU 8K USB LS PERIPH 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1318

19.0
Notes:
.
10. Total current cumulative across all Port pins flowing to Vss is limited to minimize Ground-Drop noise effects.
11. Tested under static conditions.
12. Irange: Isinkn(15)/ Isinkn(0) for the same pin.
13. Measured at cross-over point of differential data signals
14. USB Specification indicates 330 ns.
15. Tested at 200 pF.
Parameter
t
t
t
t
t
t
t
t
V
t
t
t
t
t
t
t
t
t
1.
2.
3.
4.
5.
6.
7.
8.
9.
CYC
CH
CL
r
r
f
f
rfm
drate
djr1
djr2
deop
eopr1
eopr2
eopt
udj1
udj2
crs
Functionality is guaranteed of this Vcc range, except USB transmitter, and DACs.
USB transmitter functionality is guaranteed over this Vcc range, as well as DAC outputs.
Per Table 7-6 of revision 1.0 of USB specification, for C
Port 3 bit 7 controls whether the parts goes into suspend after a POR event or waits 128ms to begin running.
POR can occur only once per applied V
V
Rx: external idle resistor, 7.5 K
Measured as largest step size vs. nominal according to measured full scale and zero programmed values.
This parameter is guaranteed, but not tested.
T
ratio
CC
ramp. Vrst is nominally 1/2 Vcc but is not specified.
= Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed.
Switching Characteristics
Input clock cycle time
Clock HIGH time
Clock LOW time
Transition Rise Time (notes 2,3,8)
Transition Rise Time (notes 2,3,8)
Transition Fall Time (notes 2,3,8)
Transition Fall Time (notes 2,3,8)
Rise/Fall Time Matching
Output Signal Crossover Voltage
Low Speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP transition Skew
EOP Width at receiver
EOP Width at receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
USB Driver Characteristics
USB Data Timing
Description
Clock
2%, to V
CLOCK
CC
, if V
CC
.
CC
drops below Vrst, POR will not re-occur. VCC must return to 0.0V before POR will be re-applied on a subsequent
LOAD
0.45 t
0.45 t
Figure 19-1. Clock Timing
1.4775
of 50 – 350 pF.
165.0
–150
Min.
1.25
–75
–45
–40
165
675
–95
1.3
75
75
80
CYC
CYC
t
CH
29
1.5225
t
168.3
Max.
CYC
1.50
300
300
120
100
150
2.0
75
45
95
t
CL
Unit
Mbs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
V
s
For Paired Transitions, (note 13)
To paired transition, Figure 19-5
Ave. Bit Rate (1.5Mb/s ± 1.5%)
Rejects as EOP, (notes 13,14)
To next transition, Figure 19-5
To Next Transition, (note 13)
Accepts as EOP, (note 13)
CLoad = 350 pF
CLoad = 350 pF
CLoad = 50 pF
CLoad = 50 pF
CY7C63411/12/13
CY7C63511/12/13
t
Conditions
r
/t
(note 13)
f
(note 15)