CY7C63723-PC Cypress Semiconductor Corp, CY7C63723-PC Datasheet - Page 40

• Manufacturer Part Number: CY7C63723-PC
• Description: IC MCU 8K LS USB/PS-2 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63723-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 10
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1322

26.0
Document #: 38-08022 Rev. *B
F
F
T
T
T
t
t
t
T
T
T
T
T
V
T
T
T
T
T
T
T
T
T
T
T
T
Notes:
Parameter
12. Initially F
13. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)
14. Tested at 200 pF.
15. Measured at cross-over point of differential data signals.
16. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.
17. SPI timing specified for capacitive load of 50 pF, with GPIO output mode = 01 (medium low drive, strong high drive).
18. Per the USB 2.0 Specification, Table 7.7, Note 10, the first transition from the Idle state is excluded.
START
WAKE
WATCH
ICLK
ICLK2
CYC
CH
CL
R
R
F
F
RFM
DRATE
DJR1
DJR2
DEOP
EOPR2
EOPT
UDJ1
UDJ2
LST
FPS2
SMCK
SSCK
CRS
Switching Characteristics
ICLK2
Internal Clock Frequency
Internal Clock Frequency, USB
mode
Input Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Time-out Delay after LVR/BOR
Internal Wake-up Period
WatchDog Timer Period
Transition Rise Time
Transition Rise Time
Transition Fall Time
Transition Fall Time
Rise/Fall Time Matching
Output Signal Crossover
Voltage
Low Speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP transition Skew Note 15
EOP Width at Receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
Width of SE0 during Diff. Transition
SDATA/SCK Transition Fall Time
SPI Master Clock Rate
SPI Slave Clock Rate
USB Driver Characteristics
= F
External Oscillator Mode
ICLK
Non-USB Mode Driver
Internal Clock Mode
[18]
USB Data Timing
until a USB packet is received.
Characteristics
Reset Timing
Description
SPI Timing
FOR
FOR
Internal Clock Mode enabled
Internal Clock Mode enabled, Bit 2 of register
0xF8h is set (Precision USB Clocking)
USB Operation, with External ±1.5%
Ceramic Resonator or Crystal
Enabled Wake-up Interrupt
F
CLoad = 200 pF (10% to 90%
CLoad = 600 pF (10% to 90%
CLoad = 200 pF (10% to 90%
CLoad = 600 pF (10% to 90%
t
CLoad = 200 to 600 pF
Ave. Bit Rate (1.5 Mb/s ±1.5%)
To Next Transition
For Paired Transitions
Accepts as EOP
To next transition, Figure 26-5
To paired transition, Figure 26-5
Note 16
CLoad = 150 pF to 600 pF
See Figures 26-6 to 26-9
F
r
/t
OSC
CLK
f
[4, 14]
/3; see Figure 17-1
= 6 MHz
[15]
Conditions
[15]
[15]
[4]
[17]
[13]
[4]
[4]
[4]
[4]
)
)
)
)
[12]
0.45 t
0.45 t
1.4775
164.2
–150
Min.
5.91
10.1
1.25
–75
–45
–40
670
–95
5.7
1.3
24
75
75
80
50
1
CYC
CYC
CY7C63722
CY7C63723
CY7C63743
1.5225
169.2
Max.
6.09
14.6
1.50
300
300
125
100
150
210
300
6.3
2.0
2.2
60
75
45
95
5
2
Page 40 of 49
Mb/s
MHz
MHz
MHz
MHz
Unit
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
%
V