CY7C63723-PC Cypress Semiconductor Corp, CY7C63723-PC Datasheet - Page 9

• Manufacturer Part Number: CY7C63723-PC
• Description: IC MCU 8K LS USB/PS-2 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63723-PC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 10
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1322

Table 8-1. I/O Register Summary (continued)
Document #: 38-08022 Rev. *B
USB Device Address
EP0 Counter Register
EP0 Mode Register
EP1 Counter Register
EP1 Mode Register
EP2 Counter Register
EP2 Mode Register
USB Status & Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer (LSB)
Timer (MSB)
WDR Clear
Capture Timer A Rising
Capture Timer A Falling
Capture Timer B Rising
Capture Timer B Falling
Capture TImer Configuration
Capture Timer Status
SPI Data
SPI Control
Clock Configuration
Processor Status & Control
Register Name
I/O Address
0x1F
0xF8
0xFF
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
0x24
0x25
0x26
0x40
0x41
0x42
0x43
0x44
0x45
0x60
0x61
FOR
FOR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
USB Endpoint 0 configuration register
USB Endpoint 1 counter register
USB Endpoint 1 configuration register
USB Endpoint 2 counter register
USB Endpoint 2 configuration register
Internal / External Clock configuration register
USB Device Address register
USB Endpoint 0 counter register
USB status and control register
Global interrupt enable register
USB endpoint interrupt enables
Lower 8 bits of free-running timer (1 MHz)
Upper 4 bits of free-running timer
Watchdog Reset clear
Rising edge Capture Timer A data register
Falling edge Capture Timer A data register
Rising edge Capture Timer B data register
Falling edge Capture Timer B data register
Capture Timer configuration register
Capture Timer status register
SPI read and write data register
SPI status and control register
Processor status and control
Function
CY7C63722
CY7C63723
CY7C63743
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14-1
14-4
14-2
14-4
14-3
14-4
14-3
13-1
21-1
21-2
18-1
18-2
19-2
19-3
19-4
19-5
19-7
19-6
17-2
17-3
20-1
Fig.
9-2
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