CY7C64013-SC Cypress Semiconductor Corp, CY7C64013-SC Datasheet - Page 24

• Manufacturer Part Number: CY7C64013-SC
• Description: IC MCU 8K FULL SPEED USB 28SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64013-SC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C640xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 19
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1327

Timer MSB
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved
12.0
Internal hardware supports communication with external devices through two interfaces: a two-wire I
a HAPI for 1, 2, or 3 byte transfers. The I
14.0, share a common configuration register (see Figure 12-1). All bits of this register are cleared on reset.
I
Note: I
Bits [7,1:0] of the HAPI/I
Bits [5:2] are used in HAPI mode only, and are described in Section 14.0. Table 12-1 shows the HAPI port configurations, and
Table 12-2 shows I
packages, and to allow simultaneous HAPI and I
HAPI operation is enabled whenever either HAPI Port Width Bit (Bit 1 or 0) is non-zero. This affects GPIO operation as described
in Section 14.0. I
Document #: 38-08001 Rev. *A
2
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
C Configuration
2
C-compatible function must be separately enabled as described in Section 13.0
I
2
C and HAPI Configuration Register
11
L3
I
2
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
2
Reserved
C Position
C-compatible blocks must be separately enabled as described in Section 13.0.
R/W
2
7
0
7
0
C pin location configuration options. These I
-
10 9
L2
2
C Configuration Register control the pin out configuration of the HAPI and I
L1 L0
Reserved
Reserved
8
6
0
6
0
-
-
7
Figure 12-1. HAPI/I
2
C-compatible interface and HAPI functions, discussed in detail in Sections 13.0 and
Reserved
Figure 11-3. Timer Block Diagram
6
LEMPTY
Figure 11-2. Timer MSB Register
Polarity
R/W
2
5
0
5
0
-
C-compatible operation.
5
4
2
Reserved
Polarity
C Configuration Register
DRDY
R/W
4
0
4
0
-
3
2
C-compatible options exist due to pin limitations in certain
2
Timer Bit 11
Empty
Latch
R
R
3
0
3
0
1
8
0
Timer Bit 10
Ready
Data
R
R
2
0
2
0
1.024-ms Interrupt
128-
1-MHz Clock
To Timer Register
2
C-compatible interface, and
HAPI Port Width
µ
s Interrupt
Timer Bit 9
2
C-compatible interfaces.
Bit 1
R/W
R
1
0
1
0
CY7C64013
CY7C64113
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HAPI Port Width
ADDRESS 0x25
ADDRESS 0x09
Timer Bit 8
Bit 0
R/W
R
0
0
0
0