668-0003-C Rabbit Semiconductor, 668-0003-C Datasheet
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Rabbit 2000 User’s Manual 019–0069 • 070831–P Microprocessor ...
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... Rabbit and Dynamic C are registered trademarks of Rabbit Semiconductor Inc. Rabbit 2000 is a trademark of Rabbit Semiconductor Inc. The latest revision of this manual is available on the Rabbit Semiconductor Web site, www.rabbit.com, for free, unregistered download. Rabbit Semiconductor Inc. ...
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Chapter 1. Introduction 1.1 Features and Specifications 1.2 Summary of Rabbit Advantages Chapter 2. Rabbit Design Features 2.1 The Rabbit 8-bit Processor vs. 16-bit and 32-bit Processors 2.2 Overview of On-Chip Peripherals 2.2.1 Serial Ports ...................................................................................................................................8 2.2.2 System Clock ...............................................................................................................................8 ...
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Chapter 4. Rabbit Capabilities 4.1 Precisely Timed Output Pulses 4.1.1 Pulse Width Modulation to Reduce Relay Power ..................................................................... 43 4.2 Open-Drain Outputs Used for Key Scan ....................................................................................................................45 4.3 Cold Boot ..............................................................................................................46 4.4 The Slave Port 4.4.1 Slave Rabbit As A ...
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Chapter 11. Timers ...................................................................................................................112 11.1 Timer A 11.1.1 Timer A I/O Registers ............................................................................................................113 11.1.2 Practical Use of Timer A .......................................................................................................114 ...................................................................................................................115 11.2 Timer B 11.2.1 Using Timer B ........................................................................................................................117 Chapter 12. Rabbit Serial Ports 12.1 Serial Port Register Layout ...................................................................................................123 ...
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Interrupt While Updating Registers ....................................................................................... 171 17.3.3 Write-only Registers Without Shadow Registers .................................................................. 172 ..............................................................................................172 17.4 Timer and Clock Usage Chapter 18. Rabbit Instructions .................................................................................................178 18.1 Load Immediate Data 18.2 Load & Store to Immediate Address 18.3 8-bit Indexed ...
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... Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium-scale controllers. The first product is the Rabbit 2000 microprocessor. The Rabbit 2000 designers have had years of experience using Z80, Z180 and HD64180 microprocessors in small controllers. The Rabbit shares a similar architecture and a high degree of compatibility with these microprocessors, but vast improvement ...
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Access to I/O devices is accomplished by using memory access instructions with an I/O prefix. Access to I/O devices is thus faster and easier compared to processors with a restricted I/O instruction set. • The hardware design rules are ...
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The built-in main clock oscillator uses an external crystal or more usually a ceramic resonator. Typical resonator frequencies are in the range of 1.8 MHz to 29.5 MHz. Since precision timing is available from the separate 32.768 kHz oscillator, ...
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Figure 1-1 shows a block diagram of the Rabbit. Figure 1-1. Block Diagram of the Rabbit Microprocessor 4 Rabbit 2000 Microprocessor User’s Manual ...
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Summary of Rabbit Advantages • The glueless architecture makes it is easy to design the hardware system. • There are a lot of serial ports and they can communicate very fast. • Precision pulse and edge generation is a ...
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Rabbit 2000 Microprocessor User’s Manual ...
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R The Rabbit is an evolutionary design. The instruction set and the register layout is that of the Z80 and Z180. The instruction set has been augmented by a substantial number of new instructions. Some obsolete or redundant Z180 ...
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The Rabbit 8-bit Processor vs. 16-bit and 32-bit Processors The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of its external 8-bit bus and ...
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Table 2-1 provides estimates of the operating power for selected clock speeds. Table 2-1. Operating Power Estimates at Selected Clock Speeds Current Clock Speed Voltage (MHz) (V) (mA) 25.0 5.0 80 12.5 5.0 40 12.5 3.3 26 6.0 3.3 13 ...
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Slave Port The slave port is designed to allow the Rabbit slave to another processor, which could be another Rabbit. The port is shared with parallel port A and is a bidirectional data port. The master ...
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There are two 10-bit match registers and compar- ators. If the match register matches the counter, a pulse is output. Thus the timer can be programmed to output a pulse at a ...
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... Standard BIOS Rabbit Semiconductor provides a standard BIOS for the Rabbit. The BIOS is a software program that manages startup and shutdown, and provides basic services for software run- ning on the Rabbit. ...
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M 3.1 Processor Registers The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are new. The EIR register is the same as the ...
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The Rabbit (and the Z80/Z180) processor has two accumulators—the A register serves as an 8-bit accumulator for 8-bit operations such as ter serves as an accumulator for 16-bit operations such as bit register DE to the 16-bit accumulator HL. For ...
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Memory Mapping Except for a handful of special instructions (see Section 18.5, “16-bit Load and Store 20- bit Address”), the Rabbit instructions directly address a 64K data memory space. This means that the address fields in the instructions are ...
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XPC register 80 STACKSEG register 79 DATASEG register D 7 SEGSIZE register Figure 3-3. Example of Memory Mapping Operation The names given to the segments in the figure are evocative of the common uses for each segment. The root ...
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The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or ...
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Extended Code Space A crucial element of the Rabbit memory mapping scheme is the ability to execute pro- grams containing megabyte of code in an efficient manner. This ability is absent in a pure 16-bit address ...
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XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the root using short jumps and calls. However, a long call must be used ...
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TCP/IP communication protocol connection where the same code accesses the data structures associated with each connection in a pat- tern determined by the traffic on each connection. The advantage of this approach is ...
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The XPC segment at the top of the memory can also be used as a data segment by pro- grams that are compiled into root memory. This is handy for small programs that need to access a lot of data. ...
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Instruction Set Outline “Load Immediate Data To a Register” on page 23 “Load or Store Data from Constant Address” on page 23 “Load or Store Data Using an Index Register” on page 24 “Register to Register ...
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Input/output instructions are now accomplished by normal memory access instructions prefixed code byte to indicate access to an I/O space. There are two I/O spaces, internal peripherals and external I/O devices. Some Z80 and Z180 instructions ...
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Load or Store Data Using an Index Register An index register is a 16-bit register, usually IX, IY HL, that is used for the address of a byte or word to be fetched from or stored to ...
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Register to Register Move Any of the 8-bit registers and L, can be moved to any other 8-bit regis- ter, for example: LD A,c LD d,b LD e,l The alternate 8-bit registers can ...
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Push and Pop Instructions There are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY. The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is exclusive to the ...
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The instruction is a special instruction designed to help test the HL register. BOOL sets HL to the value non zero, otherwise zero its value is not changed. The flags are set according ...
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The instruction can also be used to perform a sign extension. SBC ; extend sign A,l rla ; sign to carry SBC A all 1’s if sign negative LD h,a ; sign ...
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Input/Output Instructions The Rabbit uses an entirely different scheme for accessing input/output devices. Any memory access instruction may be prefixed by one of two prefixes, one for internal I/O space and one for external I/O space. When so prefixed, ...
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The bug may be easily avoided by placing a ing instruction from the above list. Rabbit users are unlikely to encounter this problem because the sequence of instructions that exhibit the bug is never generated by the Dynamic C compiler ...
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How Assembly Language—Tips and Tricks 3.4.1 Zero Clocks BOOL clocks, clears carry clocks, 4 total - get rid of possible ...
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Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation. The zero flag is set if the numbers are equal. With the SBC instruction the carry cleared is set if ...
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Some simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a reverse sense from pseudo-code in the form LD DE,(65535-B) address pointed to by 65535-B the 16-bit unsigned integer B ...
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A>B (!S & !V & ! & V) A<B (S & !V) v (!S & V & !Z) A==B A>=B A<=B Another method of doing signed compare is to first map the signed integers onto unsigned integers by ...
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Interrupt Structure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con- trol is transferred to the address of the interrupt service routine. The address of the inter- rupt service routine has ...
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... As a rule of thumb, Rabbit Semiconductor usually suggests that 100 µs be allowed for interrupt latency on Z180-based controllers. ...
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Multiple External Interrupting Devices The Rabbit has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge sensitive, meaning ...
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The privileged instructions to manipulate the IP register are listed below. IPSET 0 ; shift IP left and set priority 00 in bits 1,0 IPSET 1 IPSET 2 IPSET 3 IPRES ; rotate IP right 2 bits, restoring previous priority ...
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Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made. This would be done by the following sequence. LD xpc,a JP (HL) In this ...
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Rabbit 2000 Microprocessor User’s Manual ...
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This section describes the various capabilities of the Rabbit that may not be obvious from the technical description. 4.1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control. The effect of interrupt latency is avoided because ...
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Pulse width modulated output—The minimum pulse width is 10 µs. If the repetition rate is 10 ms, then a new pulse with 1000 different widths can be generated at the rate of 100 times per second. Asynchronous communications serial output—Asynchronous ...
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Pulse Width Modulation to Reduce Relay Power Typically relays need far less current to hold them closed than is needed to initially close them. For example, if the driver is switched to a 75% duty cycle using pulse width ...
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push af ;10 push hl ld hl,(ptr) ;11 ld a,(hl) ;5 ioi ld (port), output data inc hl ld a,0x0f ;4 and l ; see end of cycle jr z,step2 ld (ptr),hl pop hl pop ...
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Cold Boot Most microprocessors start executing at a fixed address, often address zero, after a reset or power-on condition. The Rabbit has two mode pins (SMODE0, SMODE1—see Figure 5- 1). The logic state of these two pins determines the ...
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The Slave Port The slave port allows a Rabbit to act as a slave to another processor, which can also be a Rabbit. The slave has to have only a processor chip, a RAM chip, and clock and reset ...
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Of the three registers seen by each side for each direction of communication, the first reg- ister, slave register zero, has a special function because an interrupt can only be generated by a write to this register, which then causes ...
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Rabbit 2000 Microprocessor User’s Manual ...
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SSIGNMENTS AND 5.1 Package Schematic and Pinout CLK 1 VSS 2 VDD 3 /CS2 4 /CS1 5 /OE0 6 A10 7 /CS0 ...
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Package Mechanical Dimensions Figure 5-2 shows the mechanical dimensions of the Rabbit PQFP package. Figure 5-2. Mechanical Dimensions Rabbit PQFP Package Figure 5-3 shows the PC board land pattern for the Rabbit 100-pin PQFP. This land pat- tern is ...
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Figure 5-3. PC Board Land Pattern for Rabbit 100-pin PQFP Chapter 5 Pin Assignments and Functions 51 ...
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Rabbit Pin Descriptions Table 5-1 lists all the pins on the device, along with their direction, function, and pin num- ber on the package. Table 5-1. Rabbit Pin Descriptions Pin Group Pin Name Direction CLK Output /RESET Input Hardware ...
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Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction SMODE1 Status Input SMODE0 /CS0 Output Chip Selects /CS1 Output /CS2 Output /OE0 Output Output Enables /OE1 Output /WE0 Output Write Enables /WE1 Output I/O Control /BUFEN Output Chapter ...
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Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction I/O Read /IORD Output Strobe I/O Write /IOWR Output Strobe Input/ I/O Port A PA0–PA7 Output I/O Port B PB0–PB7 6 In/2 Out I/O Port C PC0–PC7 4 In/4 ...
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Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction Input/ Output/ I/O Port D PD0–PD7 output open drain Input/ I/O Port E PE7–PE0 Output Chapter 5 Pin Assignments and Functions Function I/O Port D. Each bit may be ...
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Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction VBAT VDD Power VSS Input/ CLKA Output Input/ CLKB Output RXA, TXA, Serial Ports RX—input RXB, TXB, RXC, TXC, TX—output RXD, TXD ARXA, RX—input ATXA, ARXB, TX—output ATXB SD0-SD7 ...
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Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name Direction /I0,/I1, /I2, /I3, I/O Strobes /I4, /I5, Outputs /I6, /I7 External INT0A, Inputs Interrupt 0 INT0B External INT1A, Inputs Interrupt 1 INT1B Chapter 5 Pin Assignments and Functions Function ...
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Bus Timing The external bus has essentially the same timing for memory cycles or I/O cycles. A memory cycle begins with the chip select and the address lines. One clock later, the out- put enable is asserted for a ...
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Description of Pins with Alternate Functions Table 5-2. Pins With Alternate Functions Pin Name Output Function 1. Low on first op code fetch. STATUS (38) 2. Low on interrupt acknowledge SMODE1 (35) SMODE0 (36) 1. Peripheral clock. CLK (1) ...
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Table 5-2. Pins With Alternate Functions (continued) Pin Name Output Function CLKA (serial port A PB1 (94) clocked mode clock, bidirectional). PB0 (93) CLKB (bidirectional). PC7 (51) PC6 (54) TXA PC5 (55) PC4 (56) TXB PC3 (57) PC2 (58) TXC ...
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DC Characteristics Table 5-3. Rabbit 2000 Absolute Maximum Ratings Symbol T Operating Temperature A T Storage Temperature S Maximum Input Voltage V Maximum Operating Voltage DD Max Current Through Input Protection Diodes * The minimum voltage is -0.6 V ...
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Volts Table 5-4 outlines the DC characteristics for the Rabbit at 5.0 V over the recommended operating temperature range from T Table 5-4. 5.0 Volt DC Characteristics Symbol Parameter I Input Leakage High IH Input Leakage Low I ...
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Volts Table 5-5 outlines the DC characteristics for the Rabbit at 3.3 V over the recommended operating temperature range from T Table 5-5. 3.3 Volt DC Characteristics Symbol Parameter I Input Leakage High IH Input Leakage Low (no ...
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I/O Buffer Sourcing and Sinking Limit Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking current per pin at full AC switching speed. Full AC switching assumes 22.11 MHz CPU clock and ...
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R ABBIT 6.1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6-1. Addi- tional I/O registers were added in the Rabbit 2000 revisions as listed ...
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Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Rabbit 2000 Global Revision Register (Rev A–C) Rabbit 2000A Global Revision Register (Rev A–C) Rabbit 2000B Global Revision Register (Rev A–C) Rabbit 2000C Global Revision Register (Rev A–C) I/O Bank 0 ...
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Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Port D Data Direction Register Port D Bit 0 Register Port D Bit 1 Register Port D Bit 2 Register Port D Bit 3 Register Port D Bit 4 Register Port ...
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Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Serial Port A Status Register Serial Port A Control Register Serial Port B Data Register Serial Port B Address Register Serial Port B Status Register Serial Port B Control Register Serial ...
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Table 6-1. Rabbit Internal I/O Registers (continued) Register Name Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register Timer B Count ...
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Rabbit 2000 Microprocessor User’s Manual ...
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M ISCELLANEOUS 7.1 Processor Identification Two read-only registers are provided to allow software to identify the Rabbit microproces- sor and recognize the features and capabilities of the chip. Five bits in each of these regis- ters are unique to ...
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Rabbit Oscillators and Clocks There are two crystal oscillators built into the Rabbit. The main oscillator accepts crystals frequency of 29.4912 MHz (first overtone crystals only). The clock oscillator requires a 32.768 kHz crystal, which is ...
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Table 7-1. Global Control/Status Register (I/O adr = 0x00) Bit(s) Value 7 reset or watchdog timer timeout since the last read. The watchdog timer timed out. These bits are cleared by a read of this (read only) 01 ...
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Clock Doubler The clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide an added range of clock frequency adjustability. The clock dou- bler is controlled via the Global ...
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When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2. Oscillator Oscillator delayed and inverted Doubled clock Delay Time 0.48P Address, /CS Example Write ...
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The doubled clock is created by xor’ing the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle of the ...
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Output Pins CLK, STATUS, /WDTOUT, /BUFEN Certain output pins can have alternate assignments as specified in Table 7-4. Table 7-4. Global Output Control Register (GOCR = 0x0E) Bit(s) Value 7:6 00 CLK pin is driven with peripheral clock. 01 ...
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... The 48 bits are enough bits to count up 272 years at the 32 kHz clock frequency. By con- vention January 1, 1980, is taken as time zero. Rabbit Semiconductor software ignores the highest order bit, giving the counter a capacity of 136 years from January 1, 1980 ...
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Table 7-6. Real-Time Clock RTCxR Data Registers Bit(s) Value 7:0 Read The current value of the 48-bit RTC holding register is returned. Writing to the RTC0R transfers the current count of the RTC to six holding Write registers while the ...
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Watchdog Timer The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0. seconds, ...
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Table 7-9. Watchdog Timer Test Register (WDTTR adr = 0x09) Bit(s) Value Clock the least significant byte of the WDT timer from the peripheral 7:0 0x51 clock. (Intended for chip test and code 0x54 below only.) Clock the most significant ...
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System Reset The Rabbit has a master reset input (/RESET), which initializes everything in the device except for the RTC. This reset is delayed until the completion of any write cycles in progress to prevent any potential corruption of ...
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Table 7-10. Rabbit 2000 Reset Sequence and State of I/O Pins Pin Name Direction /RESET CLK XTALA1 XTALA2 XTALB1 XTALB2 A[19:0] D[7:0] Bidirectional /WDTOUT STATUS SMODE[1:0] /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 /BUFEN /IORD /IOWR PA[7:0] Input/Output PB[7:0] Input/Output ...
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Rabbit Interrupt Structure An interrupt causes a call to be executed, pushing the PC on the stack and starting to exe- cute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for ...
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The interrupts differ from most Z80 or Z180 interrupts in that the 256-byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16-bit pointer to the routine. The interrupt vectors are spaced ...
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External Interrupts There are two external interrupts. Because of a problem in the original Rabbit design, only one of these interrupts is available for general use. The problem was corrected in revisions A–C of the Rabbit 2000. (Refer to ...
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Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 When it is desired to expand the number of interrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou- tines. Each additional ...
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Bootstrap Operation The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the ...
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Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is ...
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Rabbit 2000 Microprocessor User’s Manual ...
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M EMORY See Section 3.2, “Memory Mapping” for a discussion of the Rabbit memory mapping. Figure 8-1 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate ...
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Boundary SEGSIZE[4..7] Boundary SEGSIZE[0..3] XPC STACKSEG DATASEG 00 + 16-bit address 20-bit address The memory management unit accepts a 16-bit address from the processor and translates it into a 20-bit address. The procedure to do this works as follows. 1. ...
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Memory Interface Unit The 20-bit memory addresses generated by the memory-mapping unit feed into the mem- ory interface unit. The memory interface unit has a separate write-only control register (see Table 8-3) for each 256K quadrant of the 1M ...
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Memory Control Unit Registers The Memory Bank Control Registers manage the physical memory space for the Rabbit 2000. There are four memory banks, where each bank is selected by the two most signifi- cant bits of the 20-bit physical ...
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MMU Instruction/Data Register 8.3.2.1 Instruction and Data Space Support Support for Instruction and Data space (I and D space) support was added in revisions A–C by optionally inverting address lines A16 and/or A19 when the processor accesses D space, ...
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Allocation of Extended Code and Data The Dynamic C compiler compiles code to root code space or to extended code space. Root code starts in low memory and compiles upward. 64K xcode window 56K Stack 52K Variables Debug Root ...
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How Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory. In ...
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Memory Figure 8-4. Compilation of Code Segments in Extended Memory 98 View in 8K window each segment Rabbit 2000 Microprocessor User’s Manual FFFF E000 FFFF E000 ...
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The Rabbit has five 8-bit parallel ports designated and E. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are ...
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Parallel Port A Parallel Port A has a single read/write register. Table 9-1. Parallel Port A Registers Register Name Port A Data Register Slave Port Control Register Table 9-2. Parallel Port A Data Register Bit Functions Bit 7 Bit ...
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Parallel Port B Parallel Port B, shown in Table 9-4, has six inputs and two outputs when used exclusively as a parallel port. Table 9-3. Parallel Port B Registers Register Name Port B Data Register Table 9-4. Parallel Port ...
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Parallel Port C Parallel port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data ...
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Parallel Port D Parallel port D, shown in Figure 9-1, has eight pins that can programmed individually to be inputs and outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. ...
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PDCR—Parallel port D control register. This register is used to control the clocking of the upper and lower nibble of the final output register of the port. On reset, bits and 5 are reset to zero. ...
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Table 9-8. Parallel Port D Registers Bit 7 Bit 6 PDDR (R/W) PD7 PD6 adr = 0x060 out = out = PDDCR (W) open open adr = 0x066 drain drain PDFR (W) x alt TXA x adr = 0x065 PDDDR ...
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Parallel Port E Parallel port E, shown in Figure 9-2, has eight I/O pins that can be individually pro- grammed as inputs or outputs. Port E has a higher drive than most of the other ports. PE7 is used ...
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Table 9-10. Parallel Port E Registers Register Name Port E Data Register Port E Control Register Port E Function Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register ...
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Table 9-11. Parallel Port E Registers Bit 7 Bit 6 PEDR (R/W) PE7 PE6 adr = 0x070 PEFR (W) alt /I7 alt /I6 adr = 0x075 PEDDR (W) dir = dir = adr = 0x077 out out PEB0R (W) x ...
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I/O B The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls the nature of the strobe and the number of wait states ...
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Compared to memory read/write cycles, which are each clock cycles long respectively, external I/O read/write cycles are always at least three clock cycles long. The eight I/O bank control registers determine the number of I/O wait states ...
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There are two timers—Timer A and Timer B. Timer A is intended mainly for generating the baud clock for the serial ports, a periodic clock for clocking parallel ports D and E, or for generating periodic interrupts. Timer B can ...
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Timer A Timer A consists of five separate countdown timers—A1 and A4–A7—as shown in Figure 11-1. Timers A1 and A4–A7 are 8-bit countdown registers as shown in Figure 11-2. The reload register can contain any number in the range ...
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When the status register is read, these bits are cleared. No bit will be lost. Either it will be read by the status register read or it will be set after ...
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The control register (TACR) is laid out as shown in Table 11-3. Table 11-3. Timer A Control Register (adr = 0x0A4) Bit 7 Bit 6 Bit Source A7 Source A6 Source A5 0-pclk/2 0-pclk/2 0-pclk/2 1-A1 ...
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Timer B Figure 11-1 shows a block diagram of Timer B. The main clock for Timer B is for Timer B. The Timer B counter can be driven directly the output of Timer A1. The first ...
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The Timer B I/O registers are listed in Table 11-4. Register Name Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Reg Timer B LSB 1 Reg Timer B MSB 2 Reg Timer B LSB 2 Reg ...
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Using Timer B Normally the prescaler is set to divide appropriate to the problem. For example, if the clock is 22.1184 MHz, then 11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of ...
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Timer B can be used for various purposes. The 10-bit counter can be read to record the time at which an event takes place. If the event creates an interrupt, the timer can be read in the interrupt routine. The ...
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Two features related to asynchronous and clocked serial communication were added to the Rabbit 2000 serial port hardware in revisions A–C to improve and simplify asynchronous serial and clocked serial communication. See Section B.2.3 for more information. The Rabbit has ...
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Serial Port Register Layout Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register, a control register and a status register. Writing to the data register starts transmis- sion. If the ...
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Table 12-1 lists the serial port registers. Table 12-1. Serial Port Registers Register Data Register Alternate Data Register to Send 9th (8th) Address Bit * Long Stop Register Status Register (read, write to clear transmit IRQ) Control Register (write only) ...
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Table 12-3 describes the serial port control registers. Table 12-3. Serial Port Control Registers (adr = 11xx0100 A,B,C,D) Bit 7,6 00—no op 00—use port C for serial 01—receive 1 byte input clocked mode (A,B) 01—use port D for ...
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Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts. There is a sepa- rate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt ...
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Transmit Serial Data Timing On transmit, if the interrupts are enabled, an interrupt is requested when the transmit regis- ter becomes empty and, in addition, an interrupt occurs when the shift register and trans- mit register both become empty, ...
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Clocked Serial Ports See Section B.2.3 for more information for more information about a new feature added to revisions A–C to better support full-duplex communication. Ports A and B can operate in clocked mode. The data line and clock ...
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Table 12-4 lists the synchronous serial port signals. Table 12-4. Synchronous Serial Port Signals Rabbit Signal Names CLKA or CLKB TxA or TxB on Parallel Port CATxA or ATxB on Parallel Port D RxA or RxB on Parallel Port C ...
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To receive a byte in external clock mode, the user must set the receive code for the ...
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Clocked Serial Timing 12.6.1 Clocked Serial Timing With Internal Clock For synchronous serial communication, the serial clock can be either generated by the Rabbit external device. The timing diagram in Figure 12-5 below can be applied ...
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Figure 12-7 shows the timing relationship among data receive. Note that RxA is sampled by the rising edge of perclk CLKA (Ext.) RxA Figure 12-7. Synchronous Serial Data Receive Timing with External Clock When clocking the Rabbit externally, the maximum ...
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At 115,200 bps, the highest speed serial port, the interrupts must be serviced in 10 baud times ...
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Controlling an RS-485 Driver and Receiver RS-485 uses a half-duplex method of communication. One station enables its driver and sends a message. After the message is complete, the station disables the driver and listens to the line for a ...
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Extra Stop Bits, Sending Parity, 9th Bit Communication Schemes Some systems may require two stop bits. In some cases, it may be necessary to send a par- ity bit. Certain systems, such as some 8051-based multidrop communications systems, use ...
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Parity, Extra Stop Bits with 8 Data Bit Characters In order to receive parity with 8 data bits, a check is made on each character for a 9th bit low. The 9th bit, or parity bit, is low if ...
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Modbus require controlling gaps between characters. Thus, it would be inadvisable to attempt Modbus with parity at a high data rate. Other ways to add a 1-baud delay are listed below: • Use another serial port as ...
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This scheme reduces the overhead associated with messages directed to other slaves, but it does not ...
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When a Rabbit microprocessor is configured as a slave, parallel port A and certain other data lines are used as communication lines between the slave and the master. The slave unit is a Rabbit configured as a slave. The master ...
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The slave port has three data registers for each direction of communication. Three regis- ters, SPD0R, SPD1R, and SPD2R, can be written by the master and read by the slave. Three different registers, also named SPD0R, SPD1R, and SPD2R, can ...
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The registers appear to be internal I/O registers to the slave. To the master, at least for a Rabbit master, the registers appear to be external I/O registers. The figure below shows the sequence of events when the master reads/writes ...
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The following table explains the parameters used in Figure 13-2. Symbol Tsu(SCS) /SCS Setup Time Th(SCS) /SCS Hold Time Tsu(SA) SA Setup Time Th(SA) SA Hold Time Tw(SRD) /SRD Low Pulse Width Ten(SRD) /SRD to SD Enable Time Ta(SRD) /SRD ...
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Master writes SPD0R Slave writes status register Slave writes SPD0R Master writes status register Figure 13-3. Slave Port Handshaking and Interrupts Figure 13-4 shows a sample connection of two slave Rabbits to a master Rabbit. The mas- ter drives the ...
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Master Rabbit D0–D7 /IORD /IOWR A0 A1 CLK portout INT0A /I7 INT1A /I6 Reset Pulldown Figure 13-4. Typical Connection Slave Rabbit to Master Rabbit The slave port lines are shown in Figure 13-1. The function of these lines is described ...
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SPD0R register. This line is set high if the master writes anything to the slave status register. This line is usually connected to cause the master to ...
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If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register, the user should be aware that all the bits might not ...
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Table 13-3 describes the slave port status register. The status register has 6 bits that are set if the particular register is full. That means that the register has been written by the processor that can write to it but ...
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Master-Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message. The protocol can be polled or interrupt driven. Generally, the master sends a message that has a message type code, perhaps ...
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As a simple example, suppose that the slave used as a four-port UART. It has the capability to send or receive characters on any of its four serial ports. Leaving aside the question of setup for parameters, ...
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The Rabbit 2000 has two built-in oscillators. The 32.768 kHz clock oscillator is needed for the battery-backable clock, the watchdog timer, and the cold-boot function. The main oscillator provides the run-time clock for the microprocessor. Figure 14-1 shows these oscillator ...
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Low-Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage. Thus, operating at 3.3 V instead will reduce the power consump- tion by a factor of 10.9/25, ...
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AC T The Rabbit 2000 processor may be operated at voltages between 2.5 V and 5.5 V, and at temperatures from –40°C to +85°C with use possible use over the range -55°C to +120°C. Most users will operate the ...
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The industrial clock speed values in Table 15-1 (at a maximum temperature of 85°C) are improved by 7% over commercial ratings at 70°C (which are extended to -40°C here). The effect of temperature alone is a clock speed that is ...
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Figure 15-1. Rabbit 2000 Typical Maximum Operating Frequency versus Temperature and 3.3 V 50.00 45.00 40.00 35.00 30.00 25.00 20.00 15.00 10.00 5.00 0.00 2 Figure ...
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Memory Access and I/O Read/Write Times The memory access time requirements are listed in Table 15- important that wait states should not be used for any memory that holds code that is being executed. Memory wait states ...
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Table 15-2. Memory Access Time Requirements (V±5%, T -40°C to +70°C) Clock Period Wait Speed States (ns) (MHz) 29.4912 34 0 27.6480 36.2 0 25.8048 38.7 0 25.8048 38.7 1 25.8048 38.7 2 24.576 40.7 0 23.9616 41.7 0 22.1184 ...
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Figure 15-3, Figure 15-4, and Figure 15-5 illustrate the memory and I/O read and write cycles. The Rabbit operates at 2 clocks per bus cycle plus any wait states that might be specified. The following memory read time delays were ...
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Figure 15-3. Memory Read and Write Cycles Notice that the data times are different, depending on whether data are being read or writ- ten. T for data read specifies how long the data must remain valid following the rising hold ...
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The following I/O read time delays were measured. Table 15-5. I/O Read Time Delays Time Delay Clock to address delay (T Clock to memory chip select delay (T Clock to I/O chip select delay (T Clock to I/O read strobe ...
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I/O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified. Figure 15-4. I/O Read and Write Cycles—No Extra Wait States Chapter 15 AC Timing Specifications 159 ...
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Figure 15-5 shows the effect of adding an extra wait state to the memory read/write cycles. The effects are similar for the I/O bus read/write cycles. Figure 15-5. Memory Read and Write with Wait States 160 Rabbit 2000 Microprocessor User’s ...
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Table 15-7 provides typical memory and external I/O parameters measured at 3.3 V. Table 15-7. Memory and External I/O Read/Write Parameters at 3.3 V Parameter Description Time from CPU clock rising T adr edge to address valid T Data read ...
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Current Consumption Typical current is proportional to both clock frequency and voltage. The main oscillator requires approximately and independent of frequency. The basic current consumption for the processor exclusive ...
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The 32.768 kHz clock oscillator and the associated real-time clock consume approxi- mately 23 µ (At 2.25 V, when backed by a battery, the current consumption is approximately 11 µA.) The (typical) current consumed when the main ...
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... BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is compiled to the target along with the application program. Rabbit Semiconductor provides the full source code for the BIOS and Virtual Driver so the user can modify them and examine details of the operation that are not apparent from the documentation ...
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... The periodic interrupt that drives the Virtual Driver occurs every 16 clocks or every 488 µs. If the 32.768 kHz oscillator is absent possible to substitute a different periodic interrupt. This alternative is not supported by Rabbit Semiconductor since the cost of connecting a crystal is very small. The periodic interrupt keeps the interrupts turned off (that is, the processor priority is raised to 1 from zero) for about 75 clocks contrib- utes little to interrupt latency ...
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The Virtual Driver’s periodic interrupt hits the hardware watchdog timer with a 2 second time-out. If ...
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O 17.1 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism. This is done by changing the clock speed or the clock doubler. The range of control is quite ...
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Reading and Writing I/O Registers The Rabbit has two I/O spaces: internal I/O registers and external I/O registers. 17.2.1 Using Assembly Language The fastest way to read and write I/O registers in Dynamic use a short ...
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Shadow Registers Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates on the chip, making possible greater capability at lower cost. Write-only registers are eas- ier to use if a memory location, called ...
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In this case, the instruction when used with an I/O prefix provides a convenient data ldd move from a memory location to an I/O location. ...
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Two library functions are provided to read and write the real-time clock: unsigned long int read_rtc(void) void write_rtc(unsigned long int time write bits 15-46 // note: bits 0-14 and bit 47 are zeroed However not intended ...
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Summary All bugs related to instructions have been fixed in revisions A–C of the Rabbit 2000 chip. See Appendix B for more information. Detailed information on instructions in provided in this chapter. “Load Immediate Data” on page 178 “8-bit Indexed ...
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Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag ALTD selects alternate flags f ALTD selects alternate flags and register fr ALTD selects alternate register r ALTD operation is a special case s IOI and IOE (“I” Column) Symbol Key Flag ...
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Symbols Rabbit Z180 Bit select: 000 = bit 0, 010 = bit 100 = bit 4, 110 = bit 6, Condition code select NZ NC, 7-bit (signed) displacement. Expressed in two’s ...
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Load Immediate Data Instruction clk A LD IX, IY, dd, r 18.2 Load & Store to Immediate Address Instruction clk A LD (mn), A,(mn (mn),HL ...
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Load and Store 20-bit Address Instruction clk A LDP (HL),HL 12 LDP (IX),HL 12 LDP (IY),HL 12 LDP HL,(HL) 10 LDP HL,(IX) 10 LDP HL,(IY) 10 LDP (mn),HL 15 LDP (mn),IX 15 LDP (mn),IY 15 LDP HL,(mn) 13 ...
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Exchange Instructions Instruction clk A EX (SP), (SP), (SP), AF,AF DE', DE',HL DE, DE,HL EXX ...
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ADD IY, ADD SP AND HL, AND IX, AND IY, BOOL BOOL BOOL DEC IX 4 DEC IY 4 DEC ss ...
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CP CP (HL (IX+ (IY+ ...
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Fast A register Operations Instruction clk A CPL 2 r NEG 4 fr RLA 2 fr RLCA 2 fr RRA 2 fr RRCA 2 fr 18.14 8-bit Shifts and Rotates RL, RLA C RLC, RLCA C RR, RRA ...
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SLA SRA (HL SRA (IX+ SRA (IY+ SRA SRL (HL SRL (IX+ SRL (IY+ SRL 18.15 Instruction Prefixes Instruction ...
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Control Instructions - Jumps and Calls Instruction clk A CALL mn 12 DJNZ (HL (IX ( LCALL xpc,mn ...
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Privileged Instructions The privileged instructions are described in this section. Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction. The three instructions below are privileged. LD SP,HL ; load the stack pointer ...
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D IFFERENCES The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. ...
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The following instructions use different register names. LD A,EIR LD EIR,A ; was I register LD IIR,A LD A,IIR ; was R register The following Z80/Z180 instructions have been dropped and are not supported. Alterna- tive Rabbit instructions are provided. ...
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I NSTRUCTIONS IN Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag ALTD selects alternate flags f ALTD selects alternate flags and register fr ALTD selects alternate register r ALTD operation is a special case s IOI and IOE (“I” ...
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Symbols Rabbit Z180 Bit select: 000 = bit 0, 010 = bit 100 = bit 4, 110 = bit 6, Condition code select NZ NC, 7-bit (signed) displacement. Expressed in two’s ...
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Instruction Byte 1 ADC A,(HL) 10001110 ADC A,(IX+d) 11011101 ADC A,(IY+d) 11111101 ADC A,n 11001110 ADC A,r 10001-r- ADC HL,ss 11101101 ADD A,(HL) 10000110 ADD A,(IX+d) 11011101 ADD A,(IY+d) 11111101 ADD A,n 11000110 ADD A,r 10000-r- ADD HL,ss 00ss1001 ADD ...
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Instruction Byte 1 EX AF,AF' 00001000 EX DE,HL 11101011 EX DE',HL 11100011 EX DE,HL' 01110110 EX DE',HL' 01110110 EXX 11011001 INC (HL) 00110100 INC (IX+d) 11011101 INC (IY+d) 11111101 INC IX 11011101 INC IY 11111101 INC r 00-r-100 INC ss ...
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Instruction Byte 1 LD A,(BC) 00001010 LD A,(DE) 00011010 LD A,(mn) 00111010 LD A,EIR 11101101 LD A,IIR 11101101 LD A,XPC 11101101 LD dd,(mn) 11101101 LD dd',BC 11101101 LD dd',DE 11101101 LD dd,mn 00dd0001 LD bc,mn 00000001 LD de,mn 00010001 LD ...
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Instruction Byte 1 LDP HL,(HL) 11101101 LDP HL,(IX) 11011101 LDP HL,(IY) 11111101 LDP HL,(mn) 11101101 LDP IX,(mn) 11011101 LDP IY,(mn) 11111101 LJP nbr,mn 11000111 LRET 11101101 MUL 11110111 NEG 11101101 NOP 00000000 OR (HL) 10110110 OR (IX+d) 11011101 OR (IY+d) ...