IC MPU RABIT3000A 55.5MHZ128LQFP

668-0011

Manufacturer Part Number668-0011
DescriptionIC MPU RABIT3000A 55.5MHZ128LQFP
ManufacturerRabbit Semiconductor
668-0011 datasheet
 


Specifications of 668-0011

Rohs StatusRoHS non-compliantProcessor TypeRabbit 3000 8-Bit
Speed55.5MHzVoltage2.5V, 2.7V, 3V, 3.3V
Mounting TypeSurface MountPackage / Case128-LQFP
Features-Other names316-1043
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Rabbit
3000 Microprocessor
User’s Manual
019-0108_W

668-0011 Summary of contents

  • Page 1

    Rabbit 3000 Microprocessor User’s Manual 019-0108_W ...

  • Page 2

    Rabbit 3000 Microprocessor User’s Manual Part Number 019-0108 ©2002–2010 Digi International Inc. • All rights reserved. Digi International reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Dynamic C are registered trademarks ...

  • Page 3

    Chapter 1. The Rabbit 3000 Processor 1.1 Introduction...........................................................................................................................................1 1.2 Features .................................................................................................................................................1 1.3 Block Diagram ......................................................................................................................................3 1.4 Basic Specifications ..............................................................................................................................4 1.5 Comparing Rabbit Microprocessors .....................................................................................................5 Chapter 2. Clocks 2.1 Overview...............................................................................................................................................7 2.1.1 Block Diagram .............................................................................................................................8 2.1.2 Registers .......................................................................................................................................8 2.2 Dependencies ........................................................................................................................................9 2.2.1 ...

  • Page 4

    Chapter 5. Memory Management 5.1 Overview ............................................................................................................................................ 39 5.1.1 Block Diagram ........................................................................................................................... 41 5.1.2 Registers .................................................................................................................................... 42 5.2 Dependencies ..................................................................................................................................... 43 5.2.1 I/O Pins ...................................................................................................................................... 43 5.2.2 Clocks ........................................................................................................................................ 43 5.2.3 Interrupts .................................................................................................................................... 43 5.3 Operation ............................................................................................................................................ 44 5.3.1 Memory ...

  • Page 5

    Chapter 10. Parallel Port C 10.1 Overview...........................................................................................................................................73 10.1.1 Block Diagram .........................................................................................................................74 10.1.2 Registers ...................................................................................................................................74 10.2 Dependencies ....................................................................................................................................74 10.2.1 I/O Pins ....................................................................................................................................74 10.2.2 Clocks .......................................................................................................................................74 10.2.3 Other Registers .........................................................................................................................74 10.2.4 Interrupts ..................................................................................................................................74 10.3 Operation ..........................................................................................................................................75 10.4 Register Descriptions ........................................................................................................................76 Chapter 11. ...

  • Page 6

    Chapter 15. Timer A 15.1 Overview ........................................................................................................................................ 107 15.1.1 Block Diagram ....................................................................................................................... 109 15.1.2 Registers ................................................................................................................................ 110 15.2 Dependencies ................................................................................................................................. 110 15.2.1 I/O Pins .................................................................................................................................. 110 15.2.2 Clocks .................................................................................................................................... 110 15.2.3 Other Registers ...................................................................................................................... 110 15.2.4 Interrupts ................................................................................................................................ 111 15.3 ...

  • Page 7

    Chapter 19. Slave Port 19.1 Overview.........................................................................................................................................157 19.1.1 Block Diagram .......................................................................................................................158 19.1.2 Registers .................................................................................................................................158 19.2 Dependencies ..................................................................................................................................159 19.2.1 I/O Pins ..................................................................................................................................159 19.2.2 Clocks .....................................................................................................................................159 19.2.3 Interrupts ................................................................................................................................159 19.3 Operation ........................................................................................................................................160 19.3.1 Master Setup ..........................................................................................................................161 19.3.2 Slave Setup .............................................................................................................................161 19.3.3 Master/Slave Communication ...

  • Page 8

    Handling Interrupts ................................................................................................................ 189 22.3.2 Example ISR .......................................................................................................................... 189 22.4 Register Descriptions ..................................................................................................................... 190 Chapter 23. External I/O Control 23.1 Overview ........................................................................................................................................ 191 23.1.1 External I/O Bus .................................................................................................................... 191 23.1.2 I/O Strobes ............................................................................................................................. 192 23.1.3 Block Diagram ....................................................................................................................... 193 ...

  • Page 9

    Enabling the System/User Mode ............................................................................................219 26.3.5 System/User Mode Instructions .............................................................................................220 26.3.6 System Mode Violation Interrupt ..........................................................................................221 26.3.7 Handling Interrupts in the System/User Mode ......................................................................222 26.4 Register Descriptions ......................................................................................................................224 Chapter 27. Specifications 27.1 DC Characteristics ..........................................................................................................................231 27.2 AC Characteristics ..........................................................................................................................233 ...

  • Page 10

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 11

    ... T HE 1.1 Introduction Rabbit Semiconductor was formed expressly to design a better microprocessor for use in small- and medium-scale single-board computers. The first microprocessors was the Rabbit 2000. Besides the Rabbit 3000, Rabbit 4000 and Rabbit 5000 microprocessors are also available. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small single-board computers ...

  • Page 12

    The high-performance instruction set offers both greater efficiency and execution speed of compiler-generated C code. Instructions include numerous single-byte opcodes that execute in two clock cycles, 16-bit and 32-bit loads and stores, 16-bit and 32-bit logical and arith- metic operations, ...

  • Page 13

    Block Diagram Figure 1-1. Rabbit 3000 Block Diagram Chapter 1 The Rabbit 3000 Processor 3 ...

  • Page 14

    Basic Specifications Table 1-1. Rabbit 3000 Specifications and Features Package Package Size Operating Voltage Operating Current Operating Temp. Maximum Clock Speed Digital I/O Serial Ports Baud Rate Address Bus Data Bus Timers Real-Time Clock RTC Oscillator Circuitry Watchdog Timer/Supervisor ...

  • Page 15

    Comparing Rabbit Microprocessors The Rabbit 2000, Rabbit 3000, Rabbit 4000, and Rabbit 5000 features are compared below. Feature Maximum Clock Speed, industrial Maximum Clock Speed, commercial Maximum Crystal Frequency Main Oscillator (may be doubled internally up to maximum clock ...

  • Page 16

    Feature External I/O Data/Address Bus Number of Serial Ports Serial Ports Capable of SPI/ Clocked Serial Serial Ports Capable of SDLC/ HDLC Asynch Serial Ports With Support for IrDA Communication Serial Ports with Support for SDLC/HDLC IrDA Communication Maximum Asynchronous ...

  • Page 17

    Overview The Rabbit 3000 supports two separate clocks—the main clock and the 32 kHz clock. The main clock is used to derive the processor clock and the peripheral clock inside the proces- sor. The 32 kHz clock is used ...

  • Page 18

    Block Diagram 2.1.2 Registers Register Name Global Control/Status Register Global Clock Modulator 0 Register Global Clock Modulator 1 Register Global Power Save Control Register Global Clock Double Register 8 I/O Mnemonic R/W Address GCSR 0x0000 R/W GCM0R 0x000A W ...

  • Page 19

    Dependencies 2.2.1 I/O Pins The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to remove problems with noise on slowly transitioning signals. The main clock disable output is on the ...

  • Page 20

    Operation 2.3.1 Main Clock The main clock is input on the CLKI pin, and is optionally sent through the spectrum spreader and then the clock doubler. Both of these are described in greater detail below. Different main clock modes ...

  • Page 21

    Spectrum Spreader When enabled, the spectrum spreader stretches and compresses the main clock in a complex pattern that spreads the energy of the clock harmonics over a wider range of frequencies. Figure 2-1. Effects of Spectrum Spreader There are ...

  • Page 22

    The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi- mum for the normal spreading and for the strong spreading. If the clock doubler is used, this ...

  • Page 23

    Clock Doubler The clock doubler allows a lower frequency crystal to be used for the main oscillator and to provide an added range over which the clock frequency can be adjusted. The clock dou- bler is controlled via the ...

  • Page 24

    When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 2-3. Oscillator Oscillator delayed and inverted Doubled clock Delay time Address / CS Example Write ...

  • Page 25

    Memory access time is not affected because the memory bus cycle is 2 clocks long and ...

  • Page 26

    Clock The 32.768 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers. If these features are not used in a design, the use of the 32 ...

  • Page 27

    The 32 kHz oscillator can be used to drive the processor and peripheral clock to provide significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided provide clock speeds as ...

  • Page 28

    Register Descriptions Global Control/Status Register Bit(s) Value 7 reset or watchdog timer timeout since the last read. (Read- 01 The watchdog timer timed out. These bits are cleared by a read of this register. only) 10 This ...

  • Page 29

    Global Clock Modulator 0 Register Bit(s) Value 0 Enable normal spectrum spreading Enable strong spectrum spreading. 6:0 These bits are reserved and should be written with zeros. Global Clock Modulator 1 Register Bit(s) Value 0 Disable the spectrum ...

  • Page 30

    Global Clock Double Register Bit(s) Value 7:4 These bits are reserved and should be written with zeros. 3:0 0000 The clock doubler circuit is disabled. 0001 6 ns nominal low time 0010 7 ns nominal low time 0011 8 ns ...

  • Page 31

    Global Output Control Register Bit(s) Value 00 CLK pin is driven by perclk. 01 CLK pin is driven by perclk/2. 7:6 10 CLK pin is low. 11 CLK pin is high. 00 STATUS pin is active (low) during a first ...

  • Page 32

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 33

    Overview The Rabbit 3000’s /RESET pin initializes everything in the processor except for the real- time clock registers write cycle is in progress, it waits until the write cycle is com- pleted to avoid potential memory corruption. ...

  • Page 34

    Registers Register Name Slave Port Control Register 3.2 Dependencies 3.2.1 I/O Pins SMODE0, SMODE1 — When the Rabbit 3000 is first powered up or when it is reset, the state of the SMODE0 and SMODE1 pins controls its operation. ...

  • Page 35

    Operation Pulling the /RESET pin low will initialize everything in the Rabbit 3000 except for the real-time clock registers. The reset of the Rabbit 3000 is delayed until the completion of any write cycles in progress; reset takes effect ...

  • Page 36

    The processor checks the SMODE pins after the /RESET signal is inactive. Table 3-2 summarizes what happens: • If both SMODE pins are zero, the Rabbit 3000 begins fetching instructions from the memory device on /CS0 and /OE0. • If ...

  • Page 37

    Register Descriptions Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write ...

  • Page 38

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 39

    Overview There are a number of basic system peripherals in the Rabbit 3000 processor, some of which are covered in later chapters. The peripherals covered in this chapter are the periodic interrupt, the real-time clock, the watchdog timers, and ...

  • Page 40

    Block Diagram 4.1.2 Registers Register Name Global Control/Status Register Real-Time Clock Control Register Real-Time Clock Byte 0 Register Real-Time Clock Byte 1 Register Real-Time Clock Byte 2 Register Real-Time Clock Byte 3 Register Real-Time Clock Byte 4 Register Real-Time ...

  • Page 41

    Dependencies 4.2.1 I/O Pins The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of these pins can be used as general-purpose outputs by driving them high or low: • the CLK pin can output the peripheral ...

  • Page 42

    Operation 4.3.1 Periodic Interrupt The following steps explain how a periodic interrupt is used. 1. Write the vector to the interrupt service routine to the internal interrupt table. 2. Enable the periodic interrupt by writing to GCSR. 3. The ...

  • Page 43

    ... The secondary watchdog timer is disabled on reset, unless the reset occurs because the primary watchdog timer times out while the secondary watchdog timer is enabled. The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing 0x005F to WDTCR. The following steps explain how to use the secondary watchdog timer ...

  • Page 44

    Register Descriptions Global Control/Status Register Bit(s) Value 7 reset or watchdog timer timeout since the last read. (Read- 01 The watchdog timer timed out. These bits are cleared by a read of this register. only) 10 This ...

  • Page 45

    Real-Time Clock Control Register Bit(s) Value Writing a 0x0000 to the RTCCR has no effect on the RTC counter. However, depending on what the previous command was, writing a 0x0000 may either 1. disable the byte increment function or 7:0 ...

  • Page 46

    Watchdog Timer Control Register Bit(s) Value 7:0 0x005A Restart the watchdog timer with a 2-second timeout period. 0x0057 Restart the watchdog timer with a 1-second timeout period. 0x0059 Restart the watchdog timer with a 500 ms timeout period. 0x0053 Restart ...

  • Page 47

    Global Output Control Register Bit(s) Value 00 CLK pin is driven by perclk. 01 CLK pin is driven by perclk/2. 7:6 10 CLK pin is low. 11 CLK pin is high. 00 STATUS pin is active (low) during a first ...

  • Page 48

    Global CPU Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. (read only) 1 Ignore the SMODE pins program fetch function. 6:5 read These bits report the state of the SMODE pins. 4:0 00001 CPU ...

  • Page 49

    Overview The Rabbit 3000 supports 8-bit external flash and SRAM devices; three chip selects and two read/write-enable strobes allow up to six external devices to be attached at once. The 8-bit mode allows wait ...

  • Page 50

    Either of the two most significant address bits (which are used to select the quadrant) can be inverted, providing the ability to bank-switch other pages from a larger memory device into the same memory bank. Code is executed in the ...

  • Page 51

    The Rabbit 2000 and 3000 have numerous instructions for reading and writing data to logical addresses, but only limited support for reading and writing data to a physical memory address. The 64 KB logical memory space limitation can also be ...

  • Page 52

    Registers Register Name MMU Instruction/Data Register Stack Segment Register Data Segment Register Segment Size Register Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register ...

  • Page 53

    Dependencies 5.2.1 I/O Pins There are three chip select pins: /CS0, /CS1, and /CS2; two read strobes, /OE0 and /OE1; and two write strobes, /WE0 and /WE1. There are eight dedicated data bus pins, D0 through D7. There are ...

  • Page 54

    Operation 5.3.1 Memory Management Unit (MMU) Code execution takes place in the 64 KB logical memory space, which is divided into four segments: root, data, stack, and extended (XMEM). The root segment is always mapped starting at physical address ...

  • Page 55

    Operation On startup Memory Bank 0 is enabled to use /CS0, /OE0, and /WE0 with four wait states and write protection enabled expected that an external flash device containing startup code be attached to those strobes. ...

  • Page 56

    It is possible to extend the timing of the /OE and/or /WE strobes by one half of a clock. This provides slightly longer strobes for slower memories; see the timing diagrams in Chapter 27. These options are available in MTCR. ...

  • Page 57

    Stack Protection (Rabbit 3000A) The ability to detect stack overflow and underflow was added starting with the Rabbit 3000A. Low and high stack limits can be set on 256-byte boundaries. When a stack- relative memory access occurs within 16 ...

  • Page 58

    Register Descriptions MMU Instruction/Data Register Bit(s) Value Internal I/O addresses are decoded using only the lower eight bits of the internal * 0 I/O address bus. This restricts internal I/O addresses to the range 0x0000– 7 0x00FF. Internal I/O ...

  • Page 59

    Data Segment Register Bit(s) Value 7:0 Read The current contents of this register are reported. Eight LSBs (MSBs are set to zero by write) of physical address offset to use if: Write SEGSIZ[3:0]  Addr[15:12] < SEGSIZ[7:4] Segment Size Register ...

  • Page 60

    MMU Expanded Code Register Bit(s) Value 7:3 These bits are reserved and should be written with zeros. Read returns zeros. 2:0 000 Normal operation. 001 This bit combination is reserved and should not be used. 010 This bit combination is ...

  • Page 61

    Stack Limit Control Register Bit(s) Value 7:1 These bits are reserved and should be written with zeros Disable stack-limit checking. 1 Enable stack-limit checking. Stack Low Limit Register Bit(s) Value Lower limit for stack-limit checking stack ...

  • Page 62

    Write-Protect Low Register Bit(s) Value 0 Disable 64K write-protect for relative address 0x70000–0x7FFFF Enable 64K write-protect for relative address 0x70000–0x7FFFF. 0 Disable 64K write-protect for relative address 0x60000–0x6FFFF Enable 64K write-protect for relative address 0x60000–0x6FFFF. 0 ...

  • Page 63

    Write-Protect High Register Bit(s) Value 0 Disable 64K write-protect for relative address 0xF0000–0xFFFFF Enable 64K write-protect for relative address 0xF0000–0xFFFFF. 0 Disable 64K write-protect for relative address 0xE0000–0xEFFFF Enable 64K write-protect for relative address 0xE0000–0xEFFFF. 0 ...

  • Page 64

    Write-Protect Segment x Low Register Bit(s) Value 7 0 Disable 4K write protect for physical address 0x7000–0x7FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x7000–0x7FFF in WP Segment Disable 4K write protect ...

  • Page 65

    Write-Protect Segment x High Register Bit(s) Value 7 0 Disable 4K write protect for physical address 0xF000–0xFFFF in WP Segment x. 1 Enable 4K write protect for physical address 0xF000–0xFFFF in WP Segment Disable 4K write protect ...

  • Page 66

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 67

    Overview The Rabbit 3000 can operate at one of four priority levels, 0–3, with Priority 0 being the expected standard operating level. The current priority and up to three previous priority levels are kept in the processor’s 8-bit IP ...

  • Page 68

    Operation To ensure proper operation, all interrupt handler routines should be written according to the following guidelines. • Push all registers to be used by the routine onto the stack before use, and pop them off the stack before ...

  • Page 69

    Table 6-2 shows the structure of the external interrupt vector table. Each interrupt vector falls on a 16-byte boundary inside the table. Table 6-2. External Interrupt Vector Table Structure Chapter 6 Interrupts Offset 0x0000+ 0x0000 External Interrupt 0 0x0010 External ...

  • Page 70

    There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3. Interrupts marked as “cleared automatically” have their requests cleared when the inter- rupt is first handled. Table 6-3. Interrupt Priorities Priority Interrupt Source Highest ...

  • Page 71

    Overview The Rabbit 3000 has two external interrupts. Each interrupt has two input pins that can be used to trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling, or both edges. The pulse needs ...

  • Page 72

    Registers Register Name Interrupt 0 Control Register Interrupt 1 Control Register 7.3 Dependencies 7.3.1 I/O Pins The external interrupts can be enabled on pins PE0, PE1, PE4, and PE5. Each pin is asso- ciated with a particular interrupt vector ...

  • Page 73

    Example ISR A sample interrupt handler is shown below. extInt_isr:: ; respond to external interrupt here ; interrupt is automatically cleared by interrupt acknowledge ipres ret 7.4.2 Expand Interrupts for Additional Peripheral Devices When you need to expand the ...

  • Page 74

    Register Descriptions Interrupt x Control Register Bit(s) Value 7:6 xx These bits are reserved for future use. 5:4 00 Parallel Port E high nibble interrupt disabled. 01 Parallel Port E high nibble interrupt on falling edge. 10 Parallel Port ...

  • Page 75

    Overview Parallel Port byte-wide port that can be used as an input or an output port. Parallel Port A is also used as the data bus for the slave port and external I/O bus. The Slave ...

  • Page 76

    Dependencies 8.2.1 I/O Pins Parallel Port A uses pins PA0 through PA7. These pins can be used as follows. • General-purpose 8-bit data input (write 0x080 to SPCR) • General-purpose 8-bit data output (write 0x084 to SPCR) • Slave ...

  • Page 77

    Register Descriptions Parallel Port A Data Register Bit(s) Value 7:0 Read The current state of Parallel Port A pins PA7–PA0 is reported. The Parallel Port A buffer is written with this value for transfer to the Parallel Write Port ...

  • Page 78

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 79

    Overview Parallel Port byte-wide port with each bit programmable for direction. The Parallel Port B pins are also used to access other peripherals on the chip—the slave port, the exter- nal I/O address bus, and clock ...

  • Page 80

    Block Diagram 9.1.2 Registers Register Name Port B Data Register Port B Data Direction Register 9.2 Dependencies 9.2.1 I/O Pins Parallel Port B uses pins PB0 through PB7. These pins can be used individually as data inputs or outputs; ...

  • Page 81

    Interrupts There are no interrupts associated with Parallel Port B. 9.3 Operation The following steps must be taken before using Parallel Port B. 1. Select the desired input/output direction for each pin via PBDDR. Note that this setting is ...

  • Page 82

    Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write These bits are ...

  • Page 83

    Overview Parallel Port byte-wide port that has four inputs and four outputs. The even-numbered ports—PC0, PC2, PC4, and PC6—are outputs. The odd-numbered ports—PC1, PC3, PC5, and PC7—are inputs.. These are simple inputs and outputs controlled and ...

  • Page 84

    Block Diagram 10.1.2 Registers Register Name Port C Data Register Port C Function Register 10.2 Dependencies 10.2.1 I/O Pins Parallel Port C uses pins PC0 through PC7. These pins can be used individually as data inputs or outputs; as ...

  • Page 85

    Operation When PCDR is read, bits and 7 return the logic level on the pin. Bits and 6 return the value of the signal driving the output buffers. The signal driving the output ...

  • Page 86

    Register Descriptions Parallel Port C Data Register Bit(s) Value 7:0 Read The current state of Parallel Port C pins PC7–PC0 is reported. The Parallel Port C buffer is written with this value for transfer to the Parallel Write Port ...

  • Page 87

    Serial Port x Control Register Bit(s) Value 7 operation. These bits are ignored in the asynch mode clocked serial mode, start a byte receive operation clocked serial mode, start a byte transmit operation. In ...

  • Page 88

    Serial Port x Control Register Bit(s) Value 00 No operation. These bits are ignored in the asynch mode clocked serial mode, start a byte receive operation. 7 clocked serial mode, start a byte transmit operation. In ...

  • Page 89

    Overview Parallel Port byte-wide port with each bit programmable individually for data direc- tion and drive level. These are simple inputs and outputs controlled and reported in the Port D Data Register (PDDR). The output registers ...

  • Page 90

    Block Diagram 11.1.2 Registers Register Name Port D Data Register Port D Control Register Port D Function Register Port D Drive Control Register Port D Data Direction Register Port D Bit 0 Register Port D Bit 1 Register Port ...

  • Page 91

    Dependencies 11.2.1 I/O Pins Parallel Port D uses pins PD0 through PD7. These pins can be used individually as data inputs or outputs, as serial port transmit and receive for Serial Ports A and PWM outputs. ...

  • Page 92

    Register Descriptions Parallel Port D Data Register Bit(s) Value 7:0 Read The current state of Parallel Port D pins PD7–PD0 is reported. The Parallel Port D buffer is written with this value for transfer to the Parallel Write Port ...

  • Page 93

    Parallel Port D Drive Control Register Bit(s) Value 7:0 0 The corresponding port bit output, is driven high and low. 1 The corresponding port bit output, is open-drain. Parallel Port D Data Direction Register Bit(s) Value ...

  • Page 94

    Parallel Port D Bit 3 Register Bit(s) Value 7:4,2:0 These bits are ignored. The port buffer (bit 3) is written with the value of this bit. The port buffer will be 3 Write transferred to the port output register on ...

  • Page 95

    Serial Port x Control Register Bit(s) Value 7 operation. These bits are ignored in the asynch mode clocked serial mode, start a byte receive operation clocked serial mode, start a byte transmit operation. In ...

  • Page 96

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 97

    Overview Parallel Port byte-wide port with each bit programmable for data direction. These are simple inputs and outputs controlled and reported in the Port E Data Register (PEDR). Each of the Parallel Port E outputs can ...

  • Page 98

    Block Diagram 12.1.2 Registers Register Name Port E Data Register Port E Control Register Port E Function Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register Port ...

  • Page 99

    Dependencies 12.2.1 I/O Pins Parallel Port E uses the pins PE0 through PE7. These pins can be used individually as data inputs or outputs external I/O strobes; four of the Parallel Port E lines can be used ...

  • Page 100

    Register Descriptions Parallel Port E Data Register Bit(s) Value 7:0 Read The current state of Parallel Port E pins PE7–PE0 is reported. The Parallel Port E buffer is written with this value for transfer to the Parallel Write Port ...

  • Page 101

    Parallel Port E Bit 0 Register Bit(s) Value 7:1 These bits are ignored. The port buffer (bit 0) is written with the value of this bit. The port buffer will be 0 Write transferred to the port output register on ...

  • Page 102

    Parallel Port E Bit 5 Register Bit(s) Value 7:6,4:0 These bits are ignored. The port buffer (bit 5) is written with the value of this bit. The port buffer will be 5 Write transferred to the port output register on ...

  • Page 103

    Interrupt x Control Register Bit(s) Value 7:6 xx These bits are reserved for future use. 5:4 00 Parallel Port E high nibble interrupt disabled. 01 Parallel Port E high nibble interrupt on falling edge. 10 Parallel Port E high nibble ...

  • Page 104

    Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write These bits are ...

  • Page 105

    Overview Parallel Port byte-wide port with each bit programmable for data direction. These are simple inputs and outputs controlled and reported in the Port F Data Register (PFDR). When used as outputs, the Parallel Port F ...

  • Page 106

    Block Diagram 13.1.2 Registers Register Name Port F Data Register Port F Control Register Port F Function Register Port F Drive Control Register Port F Data Direction Register 96 Mnemonic I/O Address PFDR 0x0038 PFCR 0x003C PFFR 0x003D PFDCR ...

  • Page 107

    Dependencies 13.2.1 I/O Pins Parallel Port F uses the pins PF0 through PF7. These pins can be used individually as data inputs or outputs clocks for Serial Ports C and D; four of the Parallel Port F ...

  • Page 108

    Register Descriptions Parallel Port F Data Register Bit(s) Value 7:0 Read The current state of Parallel Port F pins PF7–PF0 is reported. The Parallel Port F preload register is written with this value for transfer to the Write Parallel ...

  • Page 109

    Parallel Port F Drive Control Register Bit(s) Value 7:0 0 The corresponding port bit output, is driven high and low. 1 The corresponding port bit output, is open-drain. Parallel Port F Data Direction Register Bit(s) Value ...

  • Page 110

    Quad Decode Control Register Bit(s) Value Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not 00 cause Quadrature Decoder 2 to increment or decrement. 01 This bit combination is reserved and should not be used. ...

  • Page 111

    Overview Parallel Port byte-wide port with each bit programmable for data direction. These are simple inputs and outputs controlled and reported in the Port G Data Register (PGDR). When used as outputs, the Parallel Port G ...

  • Page 112

    Block Diagram 14.1.2 Registers Register Name Port G Data Register Port G Control Register Port G Function Register Port G Drive Control Register Port G Data Direction Register 14.2 Dependencies 14.2.1 I/O Pins Parallel Port G uses the pins ...

  • Page 113

    Interrupts There are no interrupts associated with Parallel Port G. 14.3 Operation The following steps must be taken before using Parallel Port G. 1. Select the desired input/output direction for each pin via PGDDR. 2. Use PGCR to select ...

  • Page 114

    Register Descriptions Parallel Port G Data Register Bit(s) Value 7:0 Read The current state of Parallel Port G pins PG7–PG0 is reported. The Parallel Port G buffer is written with this value for transfer to the Parallel Write Port ...

  • Page 115

    Parallel Port G Function Register Bit(s) Value 7 0 Parallel Port G pin 7 is always a parallel port input. 1 Parallel Port G pin 7 is enabled as RxE Parallel Port G pin parallel ...

  • Page 116

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 117

    Overview The Timer A peripheral consists of ten separate eight-bit countdown timers, A1–A10. Each counter counts down from a programmed time constant, which is automatically reloaded into the respective counter when the count reaches zero. For example, if the ...

  • Page 118

    Furthermore, these timers can- not be cascaded with Timer A1. The individual Timer A capabilities are summarized in the table below. There is a bit in the control/status register to disable all ...

  • Page 119

    Block Diagram Chapter 15 Timer A 109 ...

  • Page 120

    Registers Register Name Timer A Control/Status Register Timer A Prescale Register Timer A Time Constant 1 Register Timer A Control Register Timer A Time Constant 2 Register Timer A Time Constant 8 Register Timer A Time Constant 3 Register ...

  • Page 121

    Interrupts A Timer A interrupt can be generated whenever Timers A1–A7 decrement to zero by enabling the appropriate bit in TACSR. The interrupt request is cleared when TACSR is read. The Timer A interrupt vector is in the IIR ...

  • Page 122

    Register Descriptions Timer A Control/Status Register Bit(s) Value 7:1 0 The corresponding Timer A counter has not reached its terminal count. The corresponding Timer A counter has reached its terminal count. These status (Read- 1 bits (not the interrupt ...

  • Page 123

    Timer A Control Register Bit(s) Value 7 0 Timer A7 clocked by the main Timer A clock. 1 Timer A7 clocked by the output of Timer A1 Timer A6 clocked by the main Timer A clock. 1 Timer ...

  • Page 124

    Global Control/Status Register Bit(s) Value Processor clock from the main clock, divided by eight. 4:2 000 Peripheral clock from the main clock, divided by eight. Processor clock from the main clock, divided by eight. 001 Peripheral clock from the main ...

  • Page 125

    Overview The Timer B peripheral consists of a ten-bit free running up-counter and two match registers. Timer B is driven by perclk/2, by perclk/16 the output of Timer A1. Timer B gener- ates an output pulse whenever ...

  • Page 126

    Registers Register Name Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register Timer B Count MSB Register Timer B Count ...

  • Page 127

    Operation The following steps explain how to set up a Timer B countdown timer. 1. Select perclk/2, perclk/16, or countdown Timer A1 in TBCR. 2. Enable Timer B by writing bit 0 of TBCSR. 16.3.1 Handling ...

  • Page 128

    Register Descriptions Timer B Control/Status Register Bit(s) Value 7:3 These bits always read as zero. 2:1 0 The corresponding Timer B comparator has not encountered a match condition. The corresponding Timer B comparator has encountered a match condition. (Read- ...

  • Page 129

    Timer B Count MSB x Register Bit(s) Value Two MSBs of the compare value for the Timer B comparator. This compare 7:6 Write value will be loaded into the actual comparator when the current compare detects a match. 5:0 These ...

  • Page 130

    Global Control/Status Register Bit(s) Value Processor clock from the main clock, divided by eight. 4:2 000 Peripheral clock from the main clock, divided by eight. Processor clock from the main clock, divided by eight. 001 Peripheral clock from the main ...

  • Page 131

    Overview Serial Ports and D are identical, except for the source of the data clock and the transmit, receive, and clock pins. Serial Port A is special because it can be used to boot- strap the ...

  • Page 132

    Figure 17-1. Serial Ports A – D Operation in Clocked Serial Mode In the asynchronous mode, IrDA-compliant RZI encoding can be enabled to reduce the bit widths to 3/16 the normal width (1/8 the normal width if the serial data ...

  • Page 133

    Block Diagram Chapter 17 Serial Ports A – D 123 ...

  • Page 134

    Registers Register Name Serial Port A Data Register Serial Port A Address Register Serial Port A Long Stop Register Serial Port A Status Register Serial Port A Control Register Serial Port A Extended Register Serial Port B Data Register ...

  • Page 135

    Dependencies 17.2.1 I/O Pins Serial Port A can transmit on parallel port pins PC6 or PD6, and can receive on pins PC7 or PD7. If the clocked serial mode is enabled, the serial clock is either transmitted or received ...

  • Page 136

    Interrupts A serial port interrupt can be generated whenever a byte is available in the receive buffer or when a byte is finished being transmitted out of the transmit buffer. The serial port interrupt vectors are located in the ...

  • Page 137

    Operation 17.3.1 Asynchronous Mode The following steps explain how to set up Serial Ports A – D for asynchronous operation. The serial ports can be used by polling the status byte, but their performance will be better with an ...

  • Page 138

    Clocked Serial Mode The following steps explain how to set up Serial Ports A – D for the clocked serial mode. When the internal clock is selected, the Rabbit 3000 is in control of all transmit and receive operations. ...

  • Page 139

    A sample clocked serial interrupt handler is shown below for Serial Port B. clocked_serb_isr:: push af ioi ld a, (SASR) bit 7,a push check_for_tx rx_ready: ioi ld a, (SADR something with received byte here ld ...

  • Page 140

    Register Descriptions Serial Port x Data Register Bit(s) Value 7:0 Read Returns the contents of the receive buffer. Write Loads the transmit buffer with a data byte for transmission. Serial Port x Address Register Bit(s) Value Returns the contents ...

  • Page 141

    Serial Port x Status Register (Asynchronous Mode Only) Bit(s) Value 7 0 The receive data register is empty—no input character is ready. There is a byte in the receive buffer. The transition from “0” to “1” sets the receiver interrupt ...

  • Page 142

    Serial Port x Status Register (Clocked Serial Mode Only) Bit(s) Value 7 0 The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt 1 while this bit is set. ...

  • Page 143

    Serial Port x Control Register Bit(s) Value 7 operation. These bits are ignored in the asynchronous mode clocked serial mode, start a byte receive operation clocked serial mode, start a byte transmit operation. In ...

  • Page 144

    Serial Port x Control Register Bit(s) Value 00 No operation. These bits are ignored in the asynchronous mode clocked serial mode, start a byte receive operation. 7 clocked serial mode, start a byte transmit operation. In ...

  • Page 145

    Serial Port x Extended Register (Asynchronous Mode Only) Bit(s) Value 7:5 xxx These bits are ignored in the asynchronous mode and should be set to zeros Normal asynchronous data encoding. 1 Enable RZI coding (3/16 bit cell IrDA-compliant). ...

  • Page 146

    Serial Port x Extended Register (Clocked Serial Mode Only) Bit(s) Value 7 0 Normal clocked serial operation. 1 Timer-synchronized clocked serial operation Timer-synchronized clocked serial uses Timer B1. 1 Timer-synchronized clocked serial uses Timer B2. 5:4 00 Normal ...

  • Page 147

    Parallel Port C Function Register Bit(s) Value 7 x Parallel Port C pin 7 is always a parallel port input Parallel Port C pin parallel port output. 1 Parallel Port C pin 6 drives TxA. ...

  • Page 148

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 149

    Overview Serial Ports E and F are identical to each other, and their asynchronous operation is identi- cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes, and the ...

  • Page 150

    Several types of data encoding are available in HDLC mode: NRZ, NRZI, biphase-level (Manchester), biphase-space (FM0), and biphase-mark (FM1). IrDA-compliant RZI encoding is also available in the HDLC mode; it reduces the bit widths to one quarter the normal width, ...

  • Page 151

    Registers Register Name Serial Port E Data Register Serial Port E Address Register Serial Port E Long Stop Register Serial Port E Status Register Serial Port E Control Register Serial Port E Extended Register Serial Port F Data Register ...

  • Page 152

    Dependencies 18.2.1 I/O Pins Serial Port E can transmit on parallel port pin PG6, and can receive on pins PG7 or PG3. If the HDLC mode is enabled, the transmit serial clock is either transmitted or received on PG4, ...

  • Page 153

    Interrupts In the asynchronous mode, a serial port interrupt can be generated whenever a byte is available in the receive buffer or when a byte is finished being transmitted out of the trans- mit buffer. In the HDLC mode, ...

  • Page 154

    Operation 18.3.1 Asynchronous Mode The steps to set up Serial Ports E – F for asynchronous operation are identical to those described in Section 17.3.1 to set up Serial Ports A – D. 18.3.2 HDLC Mode The following steps ...

  • Page 155

    A sample HDLC interrupt handler is shown below for Serial Port E. hdlc_sere_isr:: push af ioi ld a, (SESR) bit 7,a push check_for_tx rx_ready: ; check status byte in A for abort or invalid CRC flags ioi ...

  • Page 156

    Several types of data encoding are available in the HDLC mode. In addition to the normal NRZ, they are NRZI, biphase-level (Manchester), biphase-space (FM0), and biphase- mark (FM1). Examples of these encodings are shown below. Note that the signal level ...

  • Page 157

    DPLL-tracked bit-cell boundaries, so the count is lengthened by either one or two counts. The decision to adjust by one or by two depends on how far off the DPLL- tracked bit cell boundaries are. This tracking ...

  • Page 158

    Figure 18-2 shows the adjustment ranges and output clock for the different modes of operation of the DPLL. Each mode of operation will be described in turn. Figure 18-2. Adjustment Ranges and Output Clock for Different DPLL Modes With NRZ ...

  • Page 159

    Biphase-mark encoding and biphase-space encoding are identical as far as the DPLL is concerned, and are similar to biphase-level encoding. The primary difference is the place- ment of the clock and data transitions. With these encodings the clock transitions are ...

  • Page 160

    Serial Port x Status Register (Asynchronous Mode Only) Bit(s) Value 7 0 The receive data register is empty—no input character is ready. There is a byte in the receive buffer. The transition from “0” to “1” sets the receiver interrupt ...

  • Page 161

    Serial Port x Status Register (HDLC Mode Only) Bit(s) Value 7 0 The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt 1 while this bit is set. The ...

  • Page 162

    Serial Port x Control Register Bit(s) Value 7 operation. These bits are ignored in the asynchronous mode the HDLC mode, force receiver in flag search mode operation the HDLC mode, transmit an ...

  • Page 163

    Serial Port x Extended Register (Asynchronous Mode Only) Bit(s) Value 7:5 xxx These bits are ignored in the asynchronous mode and should be set to zeros Normal asynchronous data encoding. 1 Enable RZI coding (3/16 bit cell IrDA-compliant). ...

  • Page 164

    Serial Port x Extended Register (HDLC Mode Only) Bit(s) Value 7:5 000 NRZ data encoding for HDLC receiver and transmitter. 010 NRZI data encoding for HDLC receiver and transmitter. 100 Biphase-level (Manchester) data encoding for HDLC receiver and transmitter. 110 ...

  • Page 165

    Parallel Port G Function Register Bit(s) Value 7 0 Parallel Port G pin 7 is always a parallel port input. 1 Parallel Port G pin 7 is enabled as RxE Parallel Port G pin parallel ...

  • Page 166

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 167

    Overview The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output regis- ters, and a status register. The data ...

  • Page 168

    The slave port can be used to bootstrap the processor by setting the SMODE pins appro- priately. See Chapter 3 for more information on this mode. 19.1.1 Block Diagram 19.1.2 Registers Register Name Slave Port Data 0 Register Slave Port ...

  • Page 169

    Dependencies 19.2.1 I/O Pins When the slave port is enabled by writing to SPCR, the following pins are enabled for slave port mode. Note that enabling the slave port mode will override any general-purpose I/O or external I/O bus ...

  • Page 170

    Operation Figure 19-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves. Figure 19-1. Master/Slave Port Connections 160 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 171

    These connections are summarized in Table 19-3. Table 19-3. Typical Slave Port Connections Master Data Bus D0–D7 Address Bus A0–A1 I/O Read Strobe /IORD I/O Write Strobe /IOWR Slave #1 Chip Select PE7 (I/O strobe I7) Slave #2 Chip Select ...

  • Page 172

    Master/Slave Communication 1. The master writes data to the appropriate external I/O address on the data bus for the slave device and register desired. For example, in the setup described here, the master would write to register SPD2R on ...

  • Page 173

    Other Configurations There are other slave port configurations possible: • The master could use the external I/O bus instead of the memory bus. • All devices could poll the slave port status register to determine when data is present ...

  • Page 174

    Timing Diagrams Figure 19-2 shows the sequence of events when the master reads/writes the slave port registers. Figure 19-2. Slave Port R/W Timing Diagram 164 Rabbit 3000 Microprocessor User’s Manual ...

  • Page 175

    The following table explains the parameters used in Figure 19-2. Symbol Tsu(SCS) /SCS Setup Time Th(SCS) /SCS Hold Time Tsu(SA) SA Setup Time Th(SA) SA Hold Time Tw(SRD) /SRD Low Pulse Width Ten(SRD) /SRD to SD Enable Time Ta(SRD) /SRD ...

  • Page 176

    Register Descriptions Slave Port Data x Registers Bit(s) Value 7:0 Read The corresponding byte of the slave port is read. Write The corresponding byte of the slave port is written. Slave Port Status Register Bit(s) Value 7 0 Processor ...

  • Page 177

    Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write These bits are ...

  • Page 178

    Rabbit 3000 Microprocessor User’s Manual ...

  • Page 179

    Overview The Input Capture peripheral consists of two channels, each of which contains a 16-bit counter and edge-detection circuitry. The Input Capture channels are usually used to deter- mine the time between events. An event is signaled by a ...

  • Page 180

    Usually it will be desired to synchronize one of the Input Capture counters with the Timer B counter. The count offset can be measured by outputting a pulse at a pre- cise time using Timer B to ...

  • Page 181

    Dependencies 20.2.1 I/O Pins Each Input Capture channel can accept input from one of the following parallel port pins: PC1, PC3, PC5, PC7, PD1, PD3, PD5, PD7, PF1, PF3, PF5, PF7, PG1, PG3, PG5, PG7. Use ICTxR to select ...

  • Page 182

    Operation 20.3.1 Input-Capture Channel The following steps explain how to set up an Input Capture channel. 1. Configure Timer A8 via TAT8R to provide the desired Input Capture clock. 2. Configure ICTxR to provide the desired start/stop operation and ...

  • Page 183

    Example Applications Pulse Width or Time Between Events The following steps explain how to measure the pulse width or time between events. 1. Select the same input pin to perform a pulse-width measurement between the start and stop conditions, ...

  • Page 184

    Register Descriptions Input Capture Control/Status Register Bit(s) Value 7 0 The Input Capture 2 Start condition has not occurred. (Read) 1 The Input Capture 2 Start condition has occurred The Input Capture 2 Stop condition has not ...

  • Page 185

    Input Capture Control Register Bit(s) Value 7:2 These bits are ignored. 1:0 00 Input Capture interrupts are disabled. 01 Input Capture interrupt use Interrupt Priority 1. 10 Input Capture interrupt use Interrupt Priority 2. 11 Input Capture interrupt use Interrupt ...

  • Page 186

    Input Capture Source x Register Bit(s) Value 7:6 00 Parallel Port C used for Start condition input. 01 Parallel Port D used for Start condition input. 10 Parallel Port F used for Start condition input. 11 Parallel Port G used ...

  • Page 187

    Q 21.1 Overview The Rabbit 3000 has a two-channel Quadrature Decoder that accepts inputs via specific pins on Parallel Port F. Each channel has two inputs, the in-phase (I) input and the 90 degree or quadrature-phase (Q) input. An ...

  • Page 188

    The Quadrature Decoders are clocked by the output of Timer A10, giving a maximum clock rate from perclk/2 down to perclk/512. The time constant of Timer A10 must be fast enough to sample the inputs properly. Both the I and ...

  • Page 189

    Block Diagram 21.1.2 Registers Register Name Quad Decode Ctrl/Status Register Quad Decode Control Register Quad Decode Count 1 Register Quad Decode Count 1 High Register Quad Decode Count 2 Register Quad Decode Count 2 High Register * Introduced with ...

  • Page 190

    Dependencies 21.2.1 I/O Pins Each Quadrature Decoder channel can accept the two encoder inputs from one of three different locations, as shown in the table below. Each channel can select a different input option. Note that these pins can ...

  • Page 191

    Operation The following steps explain how to set up a Quadrature Decoder channel. 1. Configure Timer A10 via TAT10R to provide the desired Quadrature Decoder clock speed. 2. Configure QDCR to select the input pins for the two channels. ...

  • Page 192

    Register Descriptions Quad Decode Control/Status Register Bit(s) Value 7 0 Quadrature Decoder 2 did not increment from 0xFF (0x3FF in 10-bit mode). (Read- Quadrature Decoder 2 incremented from 0xFF (0x3FF in 10-bit mode) to 0x00. 1 only) This bit ...

  • Page 193

    Quad Decode Control Register Bit(s) Value Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not 7:6 00 cause Quadrature Decoder 2 to increment or decrement. 01 This bit combination is reserved and should not be ...

  • Page 194

    Timer A Time Constant 10 Register Bit(s) Value Time constant for the Timer A counter. This time constant will take effect the 7:0 next time that the Timer A counter counts down to zero. The timer counts modulo n + ...

  • Page 195

    P 22.1 Overview The Pulse Width Modulator (PWM) consists of a 10-bit free running counter and four width registers. A PWM output consists of a train of periodic pulses within a 1024-count frame with a duty cycle that varies ...

  • Page 196

    The spreading function is implemented by dividing each 1024-clock cycle into four quad- rants of 256 clocks each. Within each quadrant, the Pulse-Width Modulator uses the eight MSBs of each pulse-width register to select the base width in each of ...

  • Page 197

    Block Diagram 22.1.2 Registers Register Name PWM LSB 0 Register PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register Chapter ...

  • Page 198

    Dependencies 22.2.1 I/O Pins Each PWM channel can be output on up one of two pins, which can be selected via the parallel port alternate output registers. 22.2.2 Clocks The PWM counter is clocked from the output of Timer ...

  • Page 199

    Operation The following steps explain how to set up a PWM channel. 1. Configure Timer A9 via TAT9R to provide the desired PWM clock frequency. 2. Configure PWLxR to select whether to spread the PWM output throughout the cycle. ...

  • Page 200

    Register Descriptions PWM LSB x Register Bit(s) Value 7:6 Write The least significant two bits for the Pulse Width Modulator count are stored Normal PWM operation. 5:4 01 Suppress PWM output seven out of eight iterations of ...