668-0011 Rabbit Semiconductor, 668-0011 Datasheet - Page 149

• Manufacturer Part Number: 668-0011
• Description: IC MPU RABIT3000A 55.5MHZ128LQFP
• Manufacturer: Rabbit Semiconductor

Specifications of 668-0011

• Rohs Status: RoHS non-compliant
• Processor Type: Rabbit 3000 8-Bit
• Speed: 55.5MHz
• Voltage: 2.5V, 2.7V, 3V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Features: -
• Other names: 316-1043

18. S
P
E – F
ERIAL
ORTS
18.1 Overview
Serial Ports E and F are identical to each other, and their asynchronous operation is identi-
cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes,
and the transmit, receive, and clock pins. Each serial port can be used in the asynchronous
or the HDLC mode with an internal or external clock.
In the asynchronous mode, either 7 or 8 data bits can be transferred, and both a parity bit
and/or an additional address (0) or long stop (1) bit can be appended as well. Parity and the
address/long stop bits are also detected when they are received. The asynchronous mode is
full-duplex.
The transmit and receive buffers of Serial Ports E and F have 4 bytes each; this reduces the
interrupt overhead requirements. A serial port interrupt is generated whenever at least one
byte is available in the receive buffer or whenever a byte is shifted out of the transmit buf-
fer. The byte is available in the buffer after the final bit is sampled.
The status of each serial port is available in the Serial Port Status Registers (SxSR), and
contains information on whether a received byte is available, the receive buffer was over-
run, a parity error was received, and the transmit buffer is empty or busy sending a byte.
The status is updated when the final bit of a received byte is sampled, or when the final bit
of a transmitted byte is sent out.
Serial Ports E and F support the HDLC mode with either an internal or an external clock;
separate pins may be used for the transmit and receive clocks, or the transmit and receive
clocks may be combined onto a single pin. The HDLC packet flag encapsulation, flag
escapes, and CRC calculation and check are handled automatically by the processor. The
serial port can detect end-of-frame, short-frame, and CRC errors. Interrupts are generated
by the reception of an end-of-frame, at the end of a transmission of a CRC, by an abort
sequence, or by a closing flag. Transmit and receive operations are essentially automatic.
16
12
5
The standard CRC-CCITT polynomial (x
+ x
+ x
+ 1) is implemented for the CRC,
with the generator and checker preset to all ones.
It is possible to send packets with or without a CRC appended. It is also possible to select
whether an abort or flag will be transmitted if the transmitter underflows. A packet under
transition can be aborted and the abort pattern sent. The idle condition of the line can be
flags or all ones.
Chapter 18 Serial Ports E – F
139