668-0011 Rabbit Semiconductor, 668-0011 Datasheet - Page 158
668-0011
Manufacturer Part Number
668-0011
Description
IC MPU RABIT3000A 55.5MHZ128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0011.pdf
(312 pages)
Specifications of 668-0011
Rohs Status
RoHS non-compliant
Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Features
-
Other names
316-1043
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Part Number:
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Figure 18-2 shows the adjustment ranges and output clock for the different modes of
operation of the DPLL. Each mode of operation will be described in turn.
Figure 18-2. Adjustment Ranges and Output Clock for Different DPLL Modes
With NRZ and NRZI encoding, all transitions occur on bit-cell boundaries and the data
should be sampled in the middle of the bit cell. If a transition occurs after the expected bit-
cell boundary (but before the midpoint), the DPLL needs to lengthen the count to line up
the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown. If
a transition occurs before the bit-cell boundary (but after the midpoint), the DPLL needs to
shorten the count to line up the bit-cell boundaries. This corresponds to the “subtract one”
and “subtract two” regions shown. The DPLL makes no adjustment if the bit-cell boundaries
are lined up within one count of the divide-by-16 counter. The regions that adjust the
count by two allow the DPLL to synchronize faster to the data stream when starting up.
With biphase-level encoding, there is a guaranteed “clock” transition at the center of every
bit cell and optional “data” transitions occur at the bit cell boundaries. The DPLL only
uses the clock transitions to track the bit-cell boundaries by ignoring all transitions occur-
ring outside a window around the center of the bit cell. This window is half a bit cell wide.
Additionally, because the clock transitions are guaranteed, the DPLL requires that they
always be present. If no transition is found in the window around the center of the bit cell
for two successive bit cells, the DPLL is not in lock and immediately enters the search
mode. The search mode assumes that the next transition seen is a clock transition and
immediately synchronizes to this transition. No clock output is provided to the receiver
during the search operation. Decoding biphase-level data requires that the data be sampled
at either the quarter or three-quarter point in the bit cell. The DPLL here uses the quarter
point to sample the data.
148
Rabbit 3000 Microprocessor User’s Manual
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