20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet
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... Rabbit 4000 Microprocessor User’s Manual 019–0152 • 070720–H ...
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... Rabbit 4000 Microprocessor User’s Manual Part Number 019-0152 • 070720–H • Printed in U.S.A. ©2006–2007 Rabbit Semiconductor Inc. • All rights reserved. No part of the contents of this manual may be reproduced or transmitted in any form or by any means without the express written permission of Rabbit Semiconductor. ...
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... I/O Pins ......................................................................................................................................11 2.2.2 Other Registers ...........................................................................................................................11 2.3 Operation ............................................................................................................................................12 2.3.1 Main Clock .................................................................................................................................12 2.3.2 Spectrum Spreader .....................................................................................................................13 2.3.3 Clock Doubler ............................................................................................................................15 2.3.4 32 kHz Clock .............................................................................................................................18 2.4 Register Descriptions ..........................................................................................................................20 Chapter 3. Reset and Bootstrap 3.1 Overview.............................................................................................................................................25 3.1.1 Block Diagram ...........................................................................................................................25 3.1.2 Registers .....................................................................................................................................26 3.2 Dependencies ......................................................................................................................................26 3.2.1 I/O Pins ......................................................................................................................................26 3.2.2 Clocks .........................................................................................................................................26 3 ...
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... Other Registers .......................................................................................................................... 74 8.2.4 Interrupts .................................................................................................................................... 74 8.3 Operation ............................................................................................................................................ 74 8.4 Register Descriptions ......................................................................................................................... 75 Chapter 9. Parallel Port B 9.1 Overview ............................................................................................................................................ 77 9.1.1 Block Diagram ........................................................................................................................... 78 9.1.2 Registers .................................................................................................................................... 78 9.2 Dependencies ..................................................................................................................................... 78 9.2.1 I/O Pins ...................................................................................................................................... 78 9.2.2 Clocks ........................................................................................................................................ 78 9.2.3 Other Registers .......................................................................................................................... 78 9.2.4 Interrupts .................................................................................................................................... 79 9.3 Operation ............................................................................................................................................ 79 9.4 Register Descriptions ......................................................................................................................... 79 Rabbit 4000 Microprocessor User’s Manual ...
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Chapter 10. Parallel Port C 10.1 Overview...........................................................................................................................................81 10.1.1 Block Diagram .........................................................................................................................82 10.1.2 Registers ...................................................................................................................................82 10.2 Dependencies ....................................................................................................................................83 10.2.1 I/O Pins ....................................................................................................................................83 10.2.2 Clocks .......................................................................................................................................83 10.2.3 Other Registers .........................................................................................................................83 10.2.4 Interrupts ..................................................................................................................................83 10.3 Operation ..........................................................................................................................................83 10.4 Register Descriptions ........................................................................................................................84 Chapter 11. ...
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... Other Registers ...................................................................................................................... 124 15.2.4 Interrupts ................................................................................................................................ 124 15.3 Operation........................................................................................................................................ 125 15.3.1 Handling Interrupts ................................................................................................................ 125 15.3.2 Example ISR .......................................................................................................................... 125 15.4 Register Descriptions ..................................................................................................................... 126 Chapter 16. Serial Ports A – D 16.1 Overview ........................................................................................................................................ 129 16.1.1 Block Diagram ....................................................................................................................... 131 16.1.2 Registers ................................................................................................................................ 132 16.2 Dependencies ................................................................................................................................. 133 16.2.1 I/O Pins .................................................................................................................................. 133 16 ...
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... Clocks .....................................................................................................................................205 20.2.3 Other Registers .......................................................................................................................205 20.2.4 Interrupts ................................................................................................................................205 20.3 Operation ........................................................................................................................................206 20.3.1 Setup .......................................................................................................................................206 20.3.2 Transmit .................................................................................................................................206 20.3.3 Receive ...................................................................................................................................206 20.3.4 Handling Interrupts ................................................................................................................207 20.3.5 Multicast Addressing .............................................................................................................208 20.4 Ethernet Interface Circuit................................................................................................................209 20.5 Register Descriptions ......................................................................................................................210 Table of Contents 173 201 ...
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... I/O Strobes ............................................................................................................................. 248 24.1.3 I/O Handshake ....................................................................................................................... 249 24.1.4 Block Diagram ....................................................................................................................... 250 24.1.5 Registers ................................................................................................................................ 250 24.2 Dependencies ................................................................................................................................. 251 24.2.1 I/O Pins .................................................................................................................................. 251 24.2.2 Clocks .................................................................................................................................... 251 24.2.3 Other Registers ...................................................................................................................... 251 24.2.4 Interrupts ................................................................................................................................ 251 Rabbit 4000 Microprocessor User’s Manual 219 231 239 247 ...
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Operation ........................................................................................................................................252 24.3.1 Auxiliary I/O Bus ...................................................................................................................252 24.3.2 I/O Strobes .............................................................................................................................252 24.3.3 I/O Handshake ........................................................................................................................252 24.4 Register Descriptions ......................................................................................................................253 Chapter 25. Breakpoints 25.1 Overview.........................................................................................................................................263 25.1.1 Block Diagram .......................................................................................................................264 25.1.2 Registers .................................................................................................................................265 25.2 Dependencies ..................................................................................................................................266 25.2.1 I/O Pins ..................................................................................................................................266 25.2.2 ...
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... A.1 Alternate Parallel Port Pin Outputs ................................................................................................. 329 A.2 Alternate Parallel Port Pin Inputs .................................................................................................... 331 Appendix B. Rabbit 4000 ESD Design Guidelines and Bug Workarounds B.1 ESD Sensitivity................................................................................................................................ 334 B.1.1 ESD Design Guidelines .......................................................................................................... 334 B.2 Bugs ................................................................................................................................................. 335 Index Rabbit 4000 Microprocessor User’s Manual 321 329 333 339 ...
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... Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small- and medium-scale single-board computers. The first microprocessors were the Rabbit 2000 and the Rabbit 3000. The latest microprocessor is the Rabbit 4000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small single-board computers ...
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... Timer 16-bit counter that counts program- mable limit. It contains eight match registers, four to set the output of a parallel-port pin and four to reset it. This allows for the creation of PWM signals (both synchronous and variable-phase) and quadrature signals. 2 Rabbit 4000 Microprocessor User’s Manual ...
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... RAM store an encryption key away from prying eyes. The Rabbit 4000 has new peripherals — DMA access and on-chip Ethernet. The Rabbit 4000 supports eight channels of DMA access to external memory, internal I/O addresses, and the auxiliary I/O bus ...
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... Block Diagram 4 Rabbit 4000 Microprocessor User’s Manual ...
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... V/3.3 V -40°C to +85°C 60 MHz 40+ (arranged in five 8-bit ports) 6 CMOS-compatible 10Base-T Clock speed/8 max. asynchronous 20/24-bit 8/16-bit Ten 8-bit, one 10-bit with 2 match registers, and one 16-bit with 8 match registers Yes, battery backable External Yes 1×, 2×, /2, /3, /4, /6, /8 ...
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... Comparing Rabbit Microprocessors The Rabbit 2000, Rabbit 3000, and Rabbit 4000 features are compared below. Feature Maximum Clock Speed, industrial Maximum Clock Speed, commercial Maximum Crystal Frequency Main Oscillator (may be doubled internally up to maximum clock speed) 32.768 kHz Crystal Oscillator ...
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... Serial Ports with Support for SDLC/ HDLC IrDA Communication Maximum Asynchronous Baud Rate Ethernet Port Input Capture Units Chapter 1 The Rabbit 4000 Processor Rabbit 4000 Rabbit 3000 Clock Speed/8 Clock Speed/8 10Base-T None 2 2 Rabbit 2000 None None Clock Speed/32 None None 7 ...
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... Rabbit 4000 Microprocessor User’s Manual ...
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... The Ethernet clock can be driven by the processor clock, the processor clock divided the input on PE6. The Ethernet clock needs MHz to conform to the 10Base-T specification. See Chapter 20 for more details on the Ethernet clock. ...
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... Register Name Global Control/Status Register Global Clock Modulator 0 Register Global Clock Modulation 1 Register Global Clock Double Register 10 Mnemonic I/O Address GCSR 0x0000 GCM0R 0x000A GCM1R 0x000B GCDR 0x000F Rabbit 4000 Microprocessor User’s Manual R/W Reset R/W 11000000 W 00000000 W 00000000 R/W 00000000 ...
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Dependencies 2.2.1 I/O Pins The main clock input is on the CLKI pin. There is an internal Schmitt trigger on this pin to remove problems with noise on slowly-transitioning signals. The main clock disable output is on the CLKIEN ...
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... CLKIEN output signal When the 32 kHz clock is enabled in GCSR, it can be further divided generate even lower frequencies by enabling those modes in bits 0–2 of GPSCR. See Table 2-4 for more details. 12 Table 2-1. Clock Modes Processor Clock ...
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... Figure 2-1. Effects of Spectrum Spreader There are three settings that correspond to normal and strong spreading in the 0–50 MHz and >50 MHz main clock range. Each setting will affect the clock cycle differently; the maximum cycle shortening (at 1.8 V and 25° ...
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... If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced. 14 Strong Spreading Normal Spreading 100 150 200 250 Frequency (MHz) Rabbit 4000 Microprocessor User’s Manual 350 300 ...
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... Table 2-3. Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value Chapter 2 Clocks Frequency Range ≤7.3728 MHz 0x0F 0x0B 7.3728–11.0592 MHz 0x09 11.0592–16.5888 MHz 0x06 16.5888–20.2752 MHz 0x03 20.2752–52.8384 MHz 0x01 52.8384–70.0416 MHz 0x00 >70.0416 MHz 15 ...
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... The times given above are for a core supply voltage of 1.8 V and a temperature of 25°C. The values increase or decrease by 1% for each 5°C increase or decrease in temperature. The doubled clock is created by xor’ing the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length ...
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However odd number of wait states is used, then the memory access time will be affected slightly The maximum allowed clock speed must be slightly reduced if the clock ...
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... The values of resistors and capacitors may need to be adjusted for various frequen- cies and crystal load capacitances. Technical Note TN235, “External 32.768 kHz Oscilla- tor Circuits“, is available on the Rabbit Semiconductor web site and goes into this circuit in detail. Figure 2-4. Basic 32.768 kHz Oscillator Circuit The 32 ...
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... The 32 kHz oscillator can be used to drive as the processor and peripheral clock to provide significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided provide clock speeds as low as 2.048 kHz. Special self-timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra-sleepy mode is enabled ...
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... Peripheral clock from the main clock, divided by 6. 1:0 00 Periodic interrupts are disabled. 01 Periodic interrupts use Interrupt Priority 1. 10 Periodic interrupts use Interrupt Priority 2. 11 Periodic interrupts use Interrupt Priority 3. 20 (GCSR) (Address = 0x0000) Description Rabbit 4000 Microprocessor User’s Manual ...
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Global Clock Modulator 0 Register Bit(s) Value Clock dither steps, from ns. Do not modify while the dither 7:6 00 function is enabled. 01 Clock dither in 0.5 ns steps, from 0 ns ...
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... Any bit combination not listed is reserved and must not be used. 22 (GCDR) (Address = 0x000F) Description Rabbit 4000 Microprocessor User’s Manual ...
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... STATUS pin is low. 11 STATUS pin is high. 3:2 00 /WDTOUT pin functions normally. 01 Enable /WDTOUT for test mode. Rabbit Semiconductor internal use only. 10 /WDTOUT pin is low (1 cycle min, 2 cycles max kHz). 11 This bit combination is reserved and should not be used. 1:0 00 /BUFEN pin is active (low) during external I/O cycles. ...
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... Force half-duplex operation. If auto-negotiation is enabled, only half-duplex 1 0 operation will be advertised. Enable full-duplex operation. If auto-negotiation is disabled, this forces full- 1 duplex operation. If auto-negotiation is enabled, this allows advertising full- duplex capability. 0 This bit is unused and should be written with zero. 24 (NACR) (Address = 0x0207) Description Rabbit 4000 Microprocessor User’s Manual ...
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... Overview The Rabbit 4000’s /RESET pin initializes everything in the processor except for the real- time clock registers and the contents of the battery-backed onchip-encryption RAM write cycle is in progress, it waits until the write cycle is completed to avoid potential memory corruption. After reset, the Rabbit 4000 checks the state of the SMODE pins. Depending on their ...
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... Pulling the /RESET pin low will initialize everything in the Rabbit 4000 except for the real-time clock registers and the onchip-encryption RAM. /CS1 — During reset the impedance of the /CS1 pin is high, and all other memory and I/O control signals are held high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the VBATIO pin (which powers /CS1) ...
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... The processor checks the SMODE pins after the /RESET signal is inactive. Table 3-2 summarizes what happens: • If both SMODE pins are zero, the Rabbit 4000 begins fetching instructions from the memory device on /CS0 and /OE0 16-bit memory is used on /CS0, the first section of code must immediately select the 16-bit bus mode ...
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... If either of the SMODE pins is high, the processor will enter the bootstrap mode and accept triplets from either Serial Port A or the slave port good practice to place pulldown resistors on the SMODE pins to ensure proper operation of your design. Table 3-2. SMODE Pin Settings ...
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Register Descriptions Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write ...
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... Rabbit 4000 Microprocessor User’s Manual ...
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... The secondary watchdog timer can time out from 30.5 µ 7.8 ms, and generates a Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt — if the secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the periodic interrupt stops occurring ...
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... RTC4R 0x0006 RTC5R 0x0007 WDTCR 0x0008 WDTTR 0x0009 SWDTR 0x000C GOCR 0x000E R/W GCPU 0x002E GREV 0x002F VRAM00– 0x0600–0x061F R/W VRAM1F Rabbit 4000 Microprocessor User’s Manual Reset 11000000 W 00000000 xxxxxxxx R xxxxxxxx R xxxxxxxx R xxxxxxxx R xxxxxxxx R xxxxxxxx W 00000000 W 00000000 W 11111111 ...
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... CLK pin can output the peripheral clock, the peripheral clock divided by two driven high or low; • the STATUS pin can be active low during the first byte of each opcode fetch, active low during an interrupt acknowledge, or driven high or low; • the /WDTOUT pin can be active low whenever the watchdog timer resets the device or driven low ...
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... The real-time clock can be reset by writing the sequence 0x40 – 0x80 to RTCCR. It can be reset and left in the byte increment mode by writing 0x40 – 0xC0 to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time clock ...
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... The secondary watchdog timer is disabled on reset, unless the reset occurs because the primary watchdog timer times out while the secondary watchdog timer is enabled. The BIOS provided by Rabbit Semiconductor in Dynamic C avoids this bug by disabling the secondary watchdog on startup or reset by writing 0x5F to WDTCR. The following steps explain how to use the secondary watchdog timer ...
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... Peripheral clock from the main clock, divided by six. 1:0 00 Periodic interrupts are disabled. 01 Periodic interrupts use Interrupt Priority 1. 10 Periodic interrupts use Interrupt Priority 2. 11 Periodic interrupts use Interrupt Priority 3. 36 (GCSR) (Address = 0x0000) Description Rabbit 4000 Microprocessor User’s Manual ...
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Real-Time Clock Control Register Bit(s) Value No effect on the real-time clock counter, or disable the byte increment function, 7:0 0x00 or cancel the real-time clock reset command. Arm the real-time clock for reset or byte increment. This command must ...
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... The timer counts modulo where n is the programmed time constant. The secondary watchdog timer can be disabled by writing the sequence 0x5A – 0x52 – 0x44 to this register. 38 ...
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... STATUS pin is low. 11 STATUS pin is high. 3:2 00 /WDTOUT pin functions normally. 01 Enable /WDTOUT for test mode. Rabbit Semiconductor internal use only. 10 /WDTOUT pin is low (1 cycle min, 2 cycles max kHz). 11 This bit combination is reserved and should not be used. 1:0 00 /BUFEN pin is active (low) during external I/O cycles. ...
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... Battery-Backed Onchip-Encryption RAM Bit(s) Value 7:0 General-purpose RAM locations. Cleared by Intrusion Detect conditions. 40 (VRAM00) (Address = 0x0600) through through (VRAM1F) (Address = 0x061F) Description Rabbit 4000 Microprocessor User’s Manual ...
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... Both 8-bit and 16-bit page-mode devices are also supported. The Rabbit 4000’s physical memory space contains four consecutive banks, each of which can be mapped to an individual chip-select/enable strobe pair. The banks can be set for equal sizes ranging from 128KB up to 4MB, providing a total physical memory range from 512KB up to 16MB ...
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... XPC register possible to run code in the XMEM window, providing an easy means of storing and executing code beyond the 64KB logical memory space. Special call and return instructions to physical addresses are provided that automatically update the XPC register as necessary. Figure 5-2. Logical and Physical Memory Mapping 42 Rabbit 4000 Microprocessor User’s Manual ...
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... The Rabbit 2000 and 3000 had numerous instructions for reading and writing data to logical addresses, but only limited support for reading and writing data to a physical memory address. This has changed for the Rabbit 4000—a wide range of instructions has been pro- vided to read and write to physical addresses possible to use the same instructions to write to logical addresses as well ...
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... WPSAR 0x0480 WPSALR 0x0481 WPSAHR 0x0482 WPSBR 0x0484 WPSBLR 0x0485 WPSBHR 0x0486 STKCR 0x0444 STKLLR 0x0445 STKHLR 0x0446 Rabbit 4000 Microprocessor User’s Manual R/W Reset R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 R/W ...
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... There are eight dedicated data bus pins, D0 through D7. If the 16-bit mode is enabled, then PD0–PD7 automatically act as the upper byte of the data bus, D8 through D15. There are 20 dedicated address pins, A0 through A19 four more address pins can be enabled on PE0–PE3, representing A20 through A23. ...
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... The data and stack segment mappings are set by writing to the appropriate register, as shown in Table 5-1. The DATASEG and STACKSEG registers provide backwards compatibility to the Rabbit 2000 and 3000 processors; these registers map directly to DATASEGL and STACKSEGL but the corresponding uppermost four bits are set to zero. ...
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Operation On startup Memory Bank 0 is enabled to use /CS0, /OE0, and /WE0 with four wait states and write protection enabled expected that an external flash device containing startup code be attached to those strobes. ...
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... Chapter 28. These options are available in MTCR possible to force /CS1 to be always active in MMIDR; enabling this will cause con- flicts only if a device shares a /OE or /WE strobe with another device. This option allows faster access to particular memory devices. 48 Rabbit 4000 Microprocessor User’s Manual ...
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Page Modes The Rabbit 4000 supports two additional memory modes to access both 16-bit and page- mode devices on /CS0 and /CS1, and can be enabled by writing to MACR. The first mode supports a 16-bit memory ...
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... Transaction Type Word Read (prefetch only) Word Write Byte Read or Write — Even Address Byte Read or Write — Odd Address All of the power-saving modes in Chapter 26 can still be used with the 16-bit mode. Because it is anticipated that the 16-bit memory may be slower than the normal 8-bit memories, separate wait-state controls for the 16-bit bus are provided in separate registers (ACS0CR and ACS1CR) ...
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Page Mode, allowing from zero to three automatic wait states for the same-page accesses in the Page Mode. The third setting selects from five to nine automatic wait states for memory-write bus cycles. The choices available for the advanced bus ...
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... The RAM segment register (RAMSR) provides a shortcut for updating code by accessing it as data. It provides a “window” that uses the instruction address decoding when read or written as data. The Rabbit 4000 Designer’s Handbook provides further details on the use of the separate instruction and data space feature ...
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... Value Internal I/O addresses are decoded using only the lower eight bits of the internal 7 0 I/O address bus. This restricts internal I/O addresses to the range 0x0000– 0x00FF. Internal I/O addresses are decoded using all 15 bits of the address internal I/O 1 address bus. This option must be selected to access internal I/O addresses of 0x0100 and higher ...
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... Four MSBs of physical address offset to use if: 3:0 SEGSIZ[3:0] <= Addr[15:12] < SEGSIZ[7:4] 54 (STKSEGL) (Address = 0x001A) Description (STKSEGH) (Address = 0x001B) Description (DATSEG) (Address = 0x0012) Description (DATSEGL) (Address = 0x001E) Description (DATSEGH) (Address = 0x001F) Description Rabbit 4000 Microprocessor User’s Manual ...
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Segment Size Register Bit(s) Value 7:0 Read The current contents of this register are reported. 7:4 Write Boundary value for switching from DATSEG to STKSEG for translation. 3:0 Write Boundary value for switching from none to DATSEG for translation. Memory ...
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... Extended timing for /WE1 (falling edge to falling edge, two clocks minimum). Normal timing for /WE0 (rising edge to falling edge, one and one-half clocks 0 0 minimum). 1 Extended timing for /WE0 (falling edge to falling edge, two clocks minimum). 56 (MECR) (Address = 0x0018) Description (MTCR) (Address = 0x0019) Description Rabbit 4000 Microprocessor User’s Manual ...
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Memory Alternate Control Register Bit(s) Value 7:6 These bits are reserved and must not be used. 5:4 00 Normal 8-bit operation for /CS1. Use MBxCR for wait states unless Page Mode. Advanced 16-bit operation for /CS1. Enable prefetch mechanism for ...
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... Disable RAM segment limit checking. 01 Select data-type MMU translation if PC[15:10] is equal to RAMSR[7:2]. 10 Select data-type MMU translation if PC[15:11] is equal to RAMSR[7:3]. 11 Select data-type MMU translation if PC[15:12] is equal to RAMSR[7:4]. 58 (ACS0CR) (Address = 0x0410) (ACS1CR) (Address = 0x0411) Description (RAMSR) (Address = 0x0448) Description Rabbit 4000 Microprocessor User’s Manual ...
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Write Protection Control Register Bit(s) Value 7:1 These bits are reserved and should be written with zeros Write protection in User Mode only. 1 Write protection in System and User modes. Chapter 5 Memory Management (WPCR) (Address = ...
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... Each write-protect register controls 8 64K blocks. Now that you have the register address, you need to know that the register bit selects the correct 64K block. This is calculated using blk64, a value between 0–255. bitnum = blk64 & 0x7 60 (WP0R) ...
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... Enable 4K write protect for physical address 0x3000–0x3FFF in WP Segment Disable 4K write protect for physical address 0x2000–0x2FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x2000–0x2FFF in WP Segment Disable 4K write protect for physical address 0x1000–0x1FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x1000– ...
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... Enable 4K write protect for physical address 0xB000–0xBFFF in WP Segment Disable 4K write protect for physical address 0xA000–0xAFFF in WP Segment x. 1 Enable 4K write protect for physical address 0xA000–0xAFFF in WP Segment Disable 4K write protect for physical address 0x9000–0x9FFF in WP Segment x. 1 Enable 4K write protect for physical address 0x9000– ...
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Stack High Limit Register Bit(s) Value Upper limit for stack-limit checking stack operation or stack-relative 7:0 memory access is attempted at an address greater than {STKHLR, 0xEF}, a stack-limit violation interrupt is generated. Chapter 5 Memory Management (STKHLR) ...
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... Rabbit 4000 Microprocessor User’s Manual ...
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... Every time an interrupt is handled or an IPSET instruction occurs, the value in the register is shifted left by two bits, and the new priority placed in bits 0–1. When an IPRES or IRET instruction occurs, the value shifted right by two bits (bits 0–1 are shifted into bits 6–7). On reset, the processor starts at Priority 3. ...
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... To ensure proper operation, all interrupt handler routines should be written according to the following guidelines. • Push all registers to be used by the routine onto the stack before use, and pop them off the stack before returning from the ISR. • Keep the ISR as short and fast as possible. ...
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... Table 6-2. External Interrupt Vector Table Structure There is a priority among interrupts if multiple requests are pending, as shown in Table 6-3. Interrupts marked as “cleared automatically” have their requests cleared when the inter- rupt is first handled. Chapter 6 Interrupts ...
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... Tx: Write to SADR, SAAR, SALR or dummy write to SASR. Rx: Read from SBDR or SBAR. Tx: Write to SBDR, SBAR, SBLR or dummy write to SBSR. Rx: Read from SCDR or SCAR. Tx: Write to SCDR, SCAR, SCLR or dummy write to SCSR. Rx: Read from SDDR or SDAR. Tx: Write to SDDR, SDAR, SDLR or dummy write to SDSR. Rabbit 4000 Microprocessor User’s Manual ...
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Overview The Rabbit 4000 has six external interrupts available, and they share two interrupt vectors. In the case of multiple interrupts sharing an interrupt vector, the data register correspond- ing to the parallel port(s) being used can be read. ...
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... Mnemonic I/O Address I0CR 0x0098 I1CR 0x0099 Register Pins I0CR PD0, PE0, PE4 I1CR PD1, PE1, PE5 Rabbit 4000 Microprocessor User’s Manual R/W Reset R/W xx000000 R/W xx000000 ...
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Register Descriptions Interrupt x Control Register Bit(s) Value 7:6 00 Parallel Port D low nibble interrupt disabled. 01 Parallel Port D low nibble interrupt on falling edge. 10 Parallel Port D low nibble interrupt on rising edge. 11 Parallel ...
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... Rabbit 4000 Microprocessor User’s Manual ...
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Overview Parallel Port byte-wide port that can be used as an input or an output port. Parallel Port A is also used as the data bus for the slave port and auxiliary I/O bus. The Slave ...
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... General-purpose 8-bit data output (write 0x084 to SPCR) • Slave port data bus (write 0x088 to SPCR) • Data bus of the auxiliary I/O bus (write 0x08C to SPCR) All Parallel Port A bits are inputs at startup or reset. See the associated peripheral chapters for details on how they use Parallel Port A. ...
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... Parallel Port A Data Register Bit(s) Value 7:0 Read The current state of Parallel Port A pins PA7–PA0 is reported. The Parallel Port A buffer is written with this value for transfer to the Parallel Write Port A output register on the next rising edge of the peripheral clock. Slave Port Control Register ...
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... Rabbit 4000 Microprocessor User’s Manual ...
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... Parallel Port byte-wide port with each bit programmable for direction. The Parallel Port B pins are also used to access other peripherals on the chip—the slave port, the auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B ...
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... Serial Ports A and B. On startup, bits 6 and 7 are outputs set low for backwards compatibility with the Rabbit 2000. All other pins are inputs. Note that when the auxiliary I/O bus or slave port is enabled in SPCR, the Parallel Port B pins associated with those peripherals perform those actions, no matter what the settings are in PBDR or PBDDR ...
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... Bit(s) Value 7:0 Read The current state of Parallel Port B pins PB7–PB0 is reported. The Parallel Port B buffer is written with this value for transfer to the Parallel Write Port B output register on the next rising edge of the peripheral clock. Parallel Port B Data Direction Register ...
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... Port B[7:0] is used for the address bus. 1:0 00 Slave port interrupts are disabled. 01 Slave port interrupts use Interrupt Priority 1. 10 Slave port interrupts use Interrupt Priority 2. 11 Slave port interrupts use Interrupt Priority 3. 80 (SPCR) (Address = 0x0024) Description Rabbit 4000 Microprocessor User’s Manual ...
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... TIMER C0 Serial Ports Input Capture A–D × RXA — — × RXB — — × RXC — — × RXD — — ORT Alt Out 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF Serial Ports E–F RXE — RCLKE TCLKE RXF — ...
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... After reset, the default condition for Parallel Port C is four outputs (the even-numbered bits) and four inputs (the odd-numbered bits). For compatibility with the Rabbit 2000 and the Rabbit 3000 microprocessors, these outputs are driven with a logic zero (low) on PC6 and a logic one (high) on PC4, PC2, and PC0. When PCDR is read, the value of the volt- age on the pin is returned ...
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... Parallel Port C uses pins PC0 through PC7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial ports A–F; as clocks for Serial Ports C–F; as external I/O strobes outputs for the PWM and Timer C periph- erals. The input capture peripheral can also watch pins PC7, PC5, PC3, and PC1. ...
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... Bit(s) Value 7:0 Read The current state of Parallel Port C pins PC7–PC0 is reported. The Parallel Port C buffer is written with this value for transfer to the Parallel Write Port C output register on the next rising edge of the peripheral clock. Parallel Port C Data Direction Register ...
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Parallel Port C Alternate High Register Bit(s) Value 7:6 00 Parallel Port C bit 7 alternate output 0 (TXA). 01 Parallel Port C bit 7 alternate output 1 (I7). 10 Parallel Port C bit 7 alternate output 2 (PWM3). 11 ...
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... Rabbit 4000 Microprocessor User’s Manual ...
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Overview Parallel Port byte-wide port with each bit programmable for data direction and drive level. These are simple inputs and outputs controlled and reported in the Port D Data Register (PDDR). All of the Parallel Port ...
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... RXB RCLKE — — TCLKE — RXC RXF DREQ1 SCLKC — DREQ0 RXD RCLKF — SCLKD TCLKF — Rabbit 4000 Microprocessor User’s Manual External Quad Interrupts Decode — — — — — — — — — QRD2A — QRD2B INT1 ...
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Block Diagram Chapter 11 Parallel Port D 89 ...
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... Parallel Port D uses pins PD0 through PD7. These pins can be used individually as data inputs or outputs; as serial port transmit and receive for Serial Ports and F; as clocks for Serial Ports C–F; as external I/O strobes outputs for the PWM and Timer C peripherals. In addition, Parallel Port D acts as the upper byte of the data bus (D[15:8]) when 16-bit addressing is enabled ...
Page 101
Other Registers Register SACR, SBCR, SCCR, SDCR, SECR, SFCR ICS1R, ICS2R QDCR I0CR, I1CR DMR0CR, DMR1CR MACR 11.2.4 Interrupts External interrupts can be accepted from pins PD1 or PD0; see Chapter 7 for more details. 11.3 Operation The following ...
Page 102
... Bit(s) Value 7:0 Read The current state of Parallel Port D pins PD7–PD0 is reported. The Parallel Port D buffer is written with this value for transfer to the Parallel Write Port D output register on the next rising edge of the peripheral clock. Parallel Port D Alternate Low Register ...
Page 103
Parallel Port D Alternate High Register Bit(s) Value 7:6 00 Parallel Port D bit 7 alternate output 0 (IA7). 01 Parallel Port D bit 7 alternate output 1 (I7). 10 Parallel Port D bit 7 alternate output 2 (PWM3). 11 ...
Page 104
... The port buffer (bit 1) is written with the value of this bit. The port buffer will be 1 Write transferred to the port output register on the next rising edge of the peripheral clock 94 (PDFR) (Address = 0x0065) Description (PDDCR) (Address = 0x0066) Description (PDDDR) (Address = 0x0067) Description (PDB0R) (Address = 0x0068) Description (PDB1R) (Address = 0x0069) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 105
Parallel Port D Bit 2 Register Bit(s) Value 7:3,1:0 These bits are ignored. The port buffer (bit 2) is written with the value of this bit. The port buffer will be 2 Write transferred to the port output register on ...
Page 106
... The port buffer (bit 7) is written with the value of this bit. The port buffer will be 7 Write transferred to the port output register on the next rising edge of the peripheral clock 96 (PDB6R) (Address = 0x006E) Description (PDB7R) (Address = 0x006F) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 107
... PE0 Chapter 12 Parallel Port E 12. P ARALLEL Alt Out 1 Alt Out 2 I7 /ACT PWM3 I6 — PWM2 I5 /LINK PWM1 I4 /A0 PWM0 I3 A23 TIMER C3 I2 A22 TIMER C2 I1 A21 TIMER C1 I0 A20 TIMER ORT Alt Out 3 SCLKC TXE RCLKE TCLKE SCLKD TXF RCLKF TCLKF 97 ...
Page 108
... RCLKE — INT1 TCLKE — INT0 RXF DREQ1 — — DREQ0 — RCLKF — INT1 TCLKF — INT0 Rabbit 4000 Microprocessor User’s Manual Quad Ethernet Decode — — — ECLK — — — — QRD2A — QRD2B — QRD1A — ...
Page 109
Block Diagram Chapter 12 Parallel Port E 99 ...
Page 110
... Serial Ports E and F; as clocks for Serial Ports C–F; as external I/O strobes; as outputs for the PWM and Timer C peripher- als; as the upper address bits A[23:20 the Ethernet clock and status LEDs for the on-chip network peripheral. The input capture peripheral can also watch pins PE7, PE5, PE3, and PE1 ...
Page 111
Other Registers Register SACR, SBCR, SCCR, SDCR, SECR, SFCR ICS1R, ICS2R QDCR I0CR, I1CR DMR0CR, DMR1CR NACR SPCR IHSR, IHTR 12.2.4 Interrupts External interrupts can be accepted from pins PE5, PE4, PE1 or PE0; see Chapter 7 for more ...
Page 112
... Bit(s) Value 7:0 Read The current state of Parallel Port E pins PE7–PE0 is reported. The Parallel Port E buffer is written with this value for transfer to the Parallel Write Port E output register on the next rising edge of the peripheral clock. Parallel Port E Alternate Low Register ...
Page 113
Parallel Port E Alternate High Register Bit(s) Value 7:6 00 Parallel Port E bit 7 alternate output 0 (I7). 01 Parallel Port E bit 7 alternate output 1 (/ACT). 10 Parallel Port E bit 7 alternate output 2 (PWM3). 11 ...
Page 114
... The port buffer (bit 1) is written with the value of this bit. The port buffer will be 1 Write transferred to the port output register on the next rising edge of the peripheral clock 104 (PEFR) (Address = 0x0075) Description (PEDCR) (Address = 0x0076) Description (PEDDR) (Address = 0x0077) Description (PEB0R) (Address = 0x0078) Description (PEB1R) (Address = 0x0079) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 115
Parallel Port E Bit 2 Register Bit(s) Value 7:3,1:0 These bits are ignored. The port buffer (bit 2) is written with the value of this bit. The port buffer will be 2 Write transferred to the port output register on ...
Page 116
... The port buffer (bit 7) is written with the value of this bit. The port buffer will be 7 Write transferred to the port output register on the next rising edge of the peripheral clock 106 (PEB6R) (Address = 0x007E) Description (PEB7R) (Address = 0x007F) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 117
... Timers A2–A7 can be used to generate baud rates for Serial Ports A–F, or they can be used as general-purpose timers if the dedicated timers on the Rabbit 4000 serial ports are used. ...
Page 118
... There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has bits for timers A1–A7 that indicate if the output pulse for that timer has taken place since the last read of the status register. These bits are cleared when the status register is read ...
Page 119
Block Diagram Chapter 13 Timer A 109 ...
Page 120
... Dependencies 13.2.1 I/O Pins The output of Timer A does not come out directly on any of the I/O pins. It can be used to control when the output occurs on Parallel Ports D–E, and can affect the output times of Serial Ports A–F and the PWM. 13.2.2 Clocks The timers in Timer A can be clocked by either perclk or perclk/2, as selected in TAPR. In addition, timers A2– ...
Page 121
... Interrupts A Timer A interrupt can be generated whenever timers A1–A7 decrement to zero by enabling the appropriate bit in TACSR. The interrupt request is cleared when TACSR is read. The Timer A interrupt vector is in the IIR at offset 0x0A0. It can be set as priority TACR. 13.3 Operation The following steps explain how to set up a Timer A timer. ...
Page 122
... These bits are reserved and should be written with zero The main clock for Timer A is the peripheral clock (perclk). 1 The main clock for Timer A is the peripheral clock divided by two (perclk/2). 112 (TACSR) (Address = 0x00A0) Description (TAPR) (Address = 0x00A1) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 123
Timer A Control Register Bit(s) Value 7 0 Timer A7 clocked by the main Timer A clock. 1 Timer A7 clocked by the output of Timer A1 Timer A6 clocked by the main Timer A clock. 1 Timer ...
Page 124
... Processor clock from the main clock, divided by four. 110 Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. 111 Peripheral clock from the main clock, divided by six. 114 (GCSR) (Address = 0x0000) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 125
Overview The Timer B peripheral consists of a ten-bit free running up-counter, two match registers, and two step registers. Timer B is driven by perclk/2, by perclk/16 the output of timer A1. Timer B generates an output ...
Page 126
... Dependencies 14.2.1 I/O Pins The output of Timer B does not come out directly on any of the I/O pins. It can be used to control when the output occurs on Parallel Ports D–E. 14.2.2 Clocks The timer in Timer B can be clocked by perclk/2, perclk/16 countdown timer A1 as selected in TBCR. ...
Page 127
... The following steps explain how to set up a Timer B countdown timer. 1. Select perclk/2, perclk/16, or countdown timer A1 in TBCR. 2. Use TBCR to select whether countdown timers B1–B2 operate normally with the match registers or whether they use the step registers to calculate match values. 3. Enable Timer B by writing bit 0 of TBCSR. ...
Page 128
... Timer B clocked by main Timer B clock divided by 8 (perclk/16). 1:0 00 Timer B interrupts are disabled. 01 Timer B interrupt use Interrupt Priority 1. 10 Timer B interrupt use Interrupt Priority 2. 11 Timer B interrupt use Interrupt Priority 3. 118 (TBCSR) (Address = 0x00B0) Description (TBCR) (Address = 0x00B1) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 129
Timer B Count MSB x Register Bit(s) Value Two MSBs of the compare value for the Timer B comparator. This compare 7:6 value will be loaded into the actual comparator when the current compare detects a match. 5:0 These bits ...
Page 130
... Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. 111 Peripheral clock from the main clock, divided by six. 120 (TBCLR) (Address = 0x00BF) Description (GCSR) (Address = 0x0000) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 131
... There are four Timer C outputs that are called Timers C0–C3. Each output is controlled by a 16-bit set value and a 16-bit reset value. Each output is set to one when the count matches the value in the corresponding set register and is cleared when the count matches the value programmed in the corresponding reset register ...
Page 132
... Block Diagram 122 Rabbit 4000 Microprocessor User’s Manual ...
Page 133
Registers Register Name Timer C Control/Status Register Timer C Control Register Timer C Divider Low Register Timer C Divider High Register Timer C Set 0 Low Register Timer C Set 0 High Register Timer C Reset 0 Low Register ...
Page 134
... PDFR, PDALR PEFR, PEALR 15.2.4 Interrupts A Timer C interrupt is enabled in TCCR, and will occur whenever the count limit value is reached. The interrupt request is cleared when TCCSR is read. 124 Function Select peripheral clock mode. Alternate port output selection Rabbit 4000 Microprocessor User’s Manual ...
Page 135
Operation The following steps explain how to set up a Timer C timer. 1. Select perclk/2, perclk/16, or countdown timer A1 in TCCR. 2. Load the desired upper limit for the counter into TCDLR and TCDHR. The overall clock ...
Page 136
... Timer C Divider High Register Bit(s) Value 7:0 The eight MSBs of the divider limit value for Timer C are stored. 126 (TCCSR) (Address = 0x0500) Description (TCCR) (Address = 0x0501) Description (TCDLR) (Address = 0x0502) Description (TCDHR) (Address = 0x0503) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 137
Timer C Set x Low Register Bit(s) Value 7:0 Eight LSBs of the match value to set Timer C Output x. Timer C Set x High Register Bit(s) Value 7:0 Eight MSBs of the match value to set Timer C ...
Page 138
... Peripheral clock from the main clock, divided by four. Processor clock from the main clock, divided by six. 111 Peripheral clock from the main clock, divided by six. 128 (TCBPR) (Address = 0x00F9) Description (GCSR) (Address = 0x0000) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 139
... The asynchronous mode is full-duplex, while the clocked mode can be half or full-duplex. Both transmit and receive have one byte of buffering — a byte may be read while another byte is being received, or the next byte to be transmitted can be loaded while the current byte is still being transferred out ...
Page 140
... Figure 16-1. Serial Ports A – D Operation in Clocked Serial Mode In the asynchronous mode, IrDA-compliant RZI encoding can be enabled to reduce the bit widths to 3/16 the normal width (1/8 the normal width if the serial data clock is 8× instead of 16×), which allows the serial port signal to be connected directly to an IrDA transceiver. ...
Page 141
... The behavior of the serial port during a break (line held low) is configurable; character assembly can continue during the break condition to allow for timing the break, or charac- ter assembly can be inhibited to reduce the interrupt overhead. 16.1.1 Block Diagram Chapter 16 Serial Ports A – D 131 ...
Page 142
... SCDHR 0x00E7 SDDR 0x00F0 SDAR 0x00F1 SDLR 0x00F2 SDSR 0x00F3 SDCR 0x00F4 SDER 0x00F5 SDDLR 0x00F6 SDDHR 0x00F7 Rabbit 4000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx W xxxxxxxx W xxxxxxxx R 0xx00000 R/W xx000000 R/W 00000000 R/W xxxxxxxx R/W 0xxxxxxx R/W ...
Page 143
... PC3 or PE3, and can be received on PD0 or PE0. NOTE: When Serial Port D is used as a clocked serial port and 8-bit memories are used, the serial clock is transmitted on PD0, and so PD0 will not be available for other use. Table 16-2. Pin Usage Serial Ports A – D Function Serial Port A ...
Page 144
... Serial Port A at offset 0x0C0 • Serial Port B at offset 0x0D0 • Serial Port C at offset 0x0E0 • Serial Port D at offset 0x0F0 Each of them can be set as Priority SxCR, where – D for the four serial ports. 134 Function Time constant for Serial Port A ...
Page 145
... Operation 16.3.1 Asynchronous Mode The following steps explain how to set up Serial Ports A – D for asynchronous operation. The serial ports can be used by polling the status byte, but their performance will be better with an interrupt. These instructions also apply to the asynchronous operation of Serial Ports E – ...
Page 146
... Clocked Serial Mode The following steps explain how to set up Serial Ports A – D for the clocked serial mode. When the internal clock is selected, the Rabbit 4000 is in control of all transmit and receive operations. When an external clock is selected the other device controls all trans- mit and receive operation ...
Page 147
... A here ioi ld (SADR), a done: pop af ipres ret Chapter 16 Serial Ports A – save used registers ; get status ; check if byte ready in RX buffer ; save status for next check ; read byte and clear interrupt ; set bits 6-7 to 01, the other bits should ...
Page 148
... Loads the transmit buffer with an address byte, marked with a “zero” address bit, for transmission. Writing the data to this register in the clocked serial mode ...
Page 149
... The transmitter is sending a byte. An interrupt is generated when the transmitter 1 clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. 1:0 00 These bits are always zero in async mode. Chapter 16 Serial Ports A – D (SASR) (Address = 0x00C3) (SBSR) (Address = 0x00D3) (SCSR) (Address = 0x00E3) ...
Page 150
... These bits are always zero in the clocked serial mode. 140 (SASR) (Address = 0x00C3) (SBSR) (Address = 0x00D3) (SCSR) (Address = 0x00E3) (SDSR) (Address = 0x00F3) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 151
... The serial port interrupt is disabled. 01 The serial port uses Interrupt Priority 1. 10 The serial port uses Interrupt Priority 2. 11 The serial port uses Interrupt Priority 3. Chapter 16 Serial Ports A – D (SACR) (Address = 0x00C4) (SBCR) (Address = 0x00D4) (SCCR) (Address = 0x00E4) (SDCR) (Address = 0x00F4) ...
Page 152
... Inhibit character assembly during break. One character (all zeros, with framing 1 error) at start and one character (garbage) at completion. 0 This bit is ignored in the asynchronous mode. 142 (SAER) (Address = 0x00C5) (SBER) (Address = 0x00D5) (SCER) (Address = 0x00E5) (SDER) (Address = 0x00F5) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 153
... Serial Port x Divider Low Register Bit(s) Value Eight LSBs of the divider that generates the serial clock for this channel. This 7:0 divider is not used unless the MSB of the corresponding SxDHR is set to one. Chapter 16 Serial Ports A – D (SAER) (Address = 0x00C5) (SBER) (Address = 0x00D5) (SCER) ...
Page 154
... Seven MSBs of the divider that generates the serial clock for this channel. 144 (SADHR) (Address = 0x00C7) (SBDHR) (Address = 0x00D7) (SCDHR) (Address = 0x00E7) (SDDHR) (Address = 0x00F7) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 155
... Serial Ports E and F are identical to each other, and their asynchronous operation is identi- cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes, and the transmit, receive, and clock pins. Each serial port can be used in the asynchronous or the HDLC mode with an internal or external clock ...
Page 156
... For more on the clock synchro- nization and data encoding, see Section 17.3.3. 17.1.1 Block Diagram 146 Rabbit 4000 Microprocessor User’s Manual ...
Page 157
... Serial Port F Address Register Serial Port F Long Stop Register Serial Port F Status Register Serial Port F Control Register Serial Port F Extended Register Serial Port F Divider Low Register Serial Port F Divider High Register Chapter 17 Serial Ports E – F Mnemonic I/O Address SEDR 0x00C8 SEAR 0x00C9 ...
Page 158
... Transmit Clock Receive Clock 17.2.2 Clocks The data clocks for Serial Ports E – F are based on the peripheral clock and divided by either a Timer A divider or a dedicated 15-bit divider. In either case, the overall clock divider will be the value in the appropriate register plus one. ...
Page 159
... The serial port interrupt vectors are located in the IIR as follows. • Serial Port E at offset 0x1C0 • Serial Port F at offset 0x1D0 Each of them can be set as Priority SxCR, where – F for the two serial ports. Chapter 17 Serial Ports E – F 149 ...
Page 160
... The receiver will be synchronized on flag bytes and will reset the CRC. By monitoring the received bytes, decisions can be made about the incoming packet not desired (i.e not addressed to this device), writing bits 6–7 of SxCR will force the receiver back into the flag search mode. ...
Page 161
... The transmitter is not capable of sending an arbitrary number of bits, but only a multiple of bytes. However, the receiver can receive frames of any bit length. If the last “byte” in the frame is not eight bits, the receiver sets a status flag that is buffered along with this last byte. Software can then use the table below to determine the number of valid data bits in this last “ ...
Page 162
... DPLL-tracked bit-cell boundaries, so the count is shortened by either one or two counts. If the transition occurs later than expected, it means that the bit-cell boundaries are late with 152 Rabbit 4000 Microprocessor User’s Manual ...
Page 163
... DPLL to provide the extra two clocks to the receiver to assemble the data correctly. The transition is specified as follows. • In the biphase-level mode this means the transition that defines the last zero of the closing flag. • In the biphase-mark and the biphase-space modes this means the transition that defines the end of the last zero of the closing flag. Chapter 17 Serial Ports E – ...
Page 164
... DPLL needs to lengthen the count to line up the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown transition occurs before the bit-cell boundary (but after the midpoint), the DPLL needs to shorten the count to line up the bit-cell boundaries. This corresponds to the “ ...
Page 165
... Read Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a “zero” address bit, Write for transmission. In the HDLC mode, the last byte of a frame must be written to this register to enable subsequent CRC and closing flag transmission. ...
Page 166
... The transmitter is sending a byte. An interrupt is generated when the transmitter 1 clears this bit, which occurs only if the transmitter is ready to start sending another byte and the transmit buffer is empty. 1:0 00 These bits are always zero in async mode. 156 (SESR) (Address = 0x00CB) (SFSR) (Address = 0x00DB) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 167
... The transmitter finished sending a closing flag. Data written in response to this 11 interrupt will cause at least two flags to be transmitted between frames The byte in the receiver buffer is 8 bits. 1 The byte in the receiver buffer is less than 8 bits. Chapter 17 Serial Ports E – F (SESR) (Address = 0x00CB) (SFSR) (Address = 0x00DB) Description 157 ...
Page 168
... The serial port interrupt is disabled. 01 The serial port uses Interrupt Priority 1. 10 The serial port uses Interrupt Priority 2. 11 The serial port uses Interrupt Priority 3. 158 (SECR) (Address = 0x00CC) (SFCR) (Address = 0x00DC) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 169
... Continue character assembly during break to allow timing the break condition. Inhibit character assembly during break. One character (all zeros, with framing 1 error) at start and one character (garbage) at completion. 0 This bit is ignored in the asynchronous mode. Chapter 17 Serial Ports E – F (SEER) (Address = 0x00CD) (SFER) (Address = 0x00DD Description ...
Page 170
... Seven MSBs of the divider that generates the serial clock for this channel. 160 (SEER) (Address = 0x00CD) (SFER) (Address = 0x00DD) Description (SEDLR) (Address = 0x00CE) (SFDLR) (Address = 0x00DE) Description (SEDHR) (Address = 0x00CF) (SFDHR) (Address = 0x00DF) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 171
Overview The slave port is a parallel communication port that can be used to communicate with an external master device. The slave port consists of three data input and data output regis- ters, and a status register. The data ...
Page 172
... Slave Port Data 2 Register Slave Port Status Register Slave Port Control Register 162 Mnemonic I/O Address SPD0R 0x0020 SPD1R 0x0021 SPD2R 0x0022 SPSR 0x0023 SPCR 0x0024 Rabbit 4000 Microprocessor User’s Manual R/W Reset R/W xxxxxxxx R/W xxxxxxxx R/W xxxxxxxx R 00000000 R/W 0xx00000 ...
Page 173
... Slave Port Pin(s) Signal PA0–PA7 SD0–SD7 PB7 /SLVATTN PB6 /SCS PB4–PB5 SA0–SA1 PB3 /SRD PB2 /SWR PE7 /SCS 18.2.2 Clocks All slave port operations are based on the processor clock. 18.2.3 Interrupts A slave port interrupt occurs on the slave device whenever the master writes to SPD0R. ...
Page 174
... Operation Figure 18-1 shows a typical slave port connection between a Rabbit processor as the master and two slaves. Figure 18-1. Master/Slave Port Connections 164 Rabbit 4000 Microprocessor User’s Manual ...
Page 175
... In this setup, the slave port is used as follows: • The slave responds to the interrupt and reads the slave port data registers. • When the slave wishes to send data to the master, it writes the slave port data registers, writing SPD0R last, which enables the /SLVATTN signal. ...
Page 176
... Rabbit 4000 Microprocessor User’s Manual ...
Page 177
... All devices could poll the slave port status register to determine when data is present instead of relying on interrupts. • The master could write to SPD0R, triggering an interrupt on the slave. The slave could then simply write a response into SPD0R, which the master detects by polling SPSR. ...
Page 178
... Timing Diagrams Figure 18-2 shows the sequence of events when the master reads/writes the slave port registers. Figure 18-2. Slave Port R/W Timing Diagram 168 Rabbit 4000 Microprocessor User’s Manual ...
Page 179
... Low Pulse Width Ten(SRD) /SRD to SD Enable Time Ta(SRD) /SRD to SD Access Time Tdis(SRD) /SRD to SD Disable Time Tsu(SRW – SRD) /SWR High to /SRD Low Setup Time Tw(SWR) /SWR Low Pulse Width Tsu(SD) SD Setup Time Th(SD) SD Hold Time Tsu(SRD – SWR) /SRD High to /SWR Low Setup Time ...
Page 180
... Slave port write byte 1 is empty. 1 Slave port write byte 1 is full Slave port write byte 0 is empty. 1 Slave port write byte 0 is full. 170 (SPD0R) (Address = 0x0020) (SPD1R) (Address = 0x0021) (SPD2R) (Address = 0x0022) Description (SPSR) (Address = 0x0023) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 181
Slave Port Control Register Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. 1 Ignore the SMODE pins program fetch function. 6:5 Read These bits report the state of the SMODE pins. Write These bits are ...
Page 182
... Rabbit 4000 Microprocessor User’s Manual ...
Page 183
... To facilitate periodic DMA transfers, there is also an internal timed request. This request is generated from a programmable 16-bit counter and may be assigned to any DMA channel the case of the external requests, this request is “ANDed” with any internal or exter- nal request that is also assigned to that DMA channel. This periodic request can be pro- grammed to transfer one byte or an entire buffer ...
Page 184
... DMA channel itself. Buffer descriptors may be used singly, to transfer one block of data, or they may be linked together for “scatter-gather” operation. Each DMA channel also contains an “initial address” that points to the first buffer descriptor in memory and allows the DMA channel to rewind itself automatically in the case of a transmit retry by the network port ...
Page 185
... DMA transfer request will be resolved in favor of the DMA transfer request. The DMA and Ethernet peripherals were optimized to work together; if the Rabbit 4000’s built-in Ethernet peripheral is used it is expected that two DMA channels will be dedicated for that purpose. ...
Page 186
... DMA y Destination Address [15:8] Register DMA y Destination Address [23:16] Register DMA y Link Address [7:0] Register DMA y Link Address [15:8] Register DMA y Link Address [23:16] Register NOTE: The y in “DMA y …” expresses the DMA channel number (0–7). 176 Mnemonic I/O Address DMCSR ...
Page 187
Dependencies 19.2.1 I/O Pins External DMA Request 0 can be enabled from pins PD2, PE2, or PE6. External DMA Request 1 can be enabled from pins PD3, PE3, or PE7. The DMA can use either the memory management unit ...
Page 188
... The descriptor can be either bytes in length; a bit in the channel control byte (which corresponds to DyCR) selects whether the link address is present or not. The pro- cessor skips the read of those bytes if a 12-byte descriptor is selected, and always skips the reads of the bytes marked “not used.” Table 19-1. DMA Buffer Descriptor Byte 0 Bytes 0– ...
Page 189
... DMA can operate. This is handled in several ways. First of all, the DMA transfers can be set to take place whenever the processor is operating at one of the four priority levels, 0–3 (note that there is a single priority level for all DMA transfers). Setting an interrupt priority to something greater than the DMA transfer priority will ensure that no DMA activity occurs during that interrupt handler ...
Page 190
... Total Clocks = 4 × Number of Bytes per Burst + 7 (for overhead) 180 Clocks per Byte Total Clocks Transferred 11 clocks 11 15 clocks 7.5 19 clocks 6.3 23 clocks 5.8 39 clocks 4.9 71 clocks 4.4 135 clocks 4.2 263 clocks 4.1 Rabbit 4000 Microprocessor User’s Manual ...
Page 191
... DMA request pending, the current transfer will be terminated and the new channel’s transfer will start. With this setting, DMA Channel 7 will always have priority over all other channels, and DMA Channel 0 will transfer only if no other channels have pending requests. The other two settings rotate the priority between channels as shown in Table 19-4 ...
Page 192
... The simplest version of the buffer array is a double buffer, which is frequently used to provide a reserve buffer in case the application is slow in handling the first buffer once received (in this case, both buffers are enabled to interrupt on completion). 182 Rabbit 4000 Microprocessor User’s Manual ...
Page 193
Linked List A linked list is similar to a buffer array, except that 16-byte descriptors are used and the descriptors are not necessarily adjacent in memory. The advantage of this mode is the ability to spread descriptors. Chapter 19 ...
Page 194
... This method allows for continuous reception of transfers with- out having to reload the initial address for the DMA buffer descriptor sequence. The “ping-pong buffer,” where there are only two buffers, is the simplest version of a circular queue. The application can operate on one buffer while the other buffer is being loaded ...
Page 195
... The current DMA buffer has been marked with “special treatment for last byte.” • The buffer has not been marked as “final buffer.” • The DMA fills the transmit FIFO with the next-to-last byte of the buffer and then either switches to another channel or releases the bus. ...
Page 196
... Always mark the buffer that contains the end-of-frame byte as the final buffer, and restart the DMA once that buffer has been transmitted. • Make sure that the DMA will not return to this channel before the transmitter has sent one byte from the transmit FIFO. ...
Page 197
Register Descriptions DMA Master Control/Status Register Bit(s) Value 7 effect on the corresponding DMA channel. Start (or restart) the corresponding DMA channel using the contents of the DMA (Write- channel registers. This command should only be issued ...
Page 198
... DMA interrupts use Interrupt Priority 3. 188 (D0BCR) (Address = 0x0103) (D1BCR) (Address = 0x0113) (D2BCR) (Address = 0x0123) (D3BCR) (Address = 0x0133) (D4BCR) (Address = 0x0143) (D5BCR) (Address = 0x0153) (D6BCR) (Address = 0x0163) (D7BCR) (Address = 0x0173) Description (DMCR) (Address = 0x0104) Description Rabbit 4000 Microprocessor User’s Manual ...
Page 199
DMA Master Timing Control Register Bit(s) Value 7:6 0x Fixed DMA channel priority. Higher channel number has higher priority. Rotating DMA channel priority. Priority rotates highest channel number to 10 lowest channel number after every byte is transferred. Rotating DMA ...
Page 200
... External DMA Request 0 supplied to DMA Channel 3. 100 External DMA Request 0 supplied to DMA Channel 4. 101 External DMA Request 0 supplied to DMA Channel 5. 110 External DMA Request 0 supplied to DMA Channel 6. 111 External DMA Request 0 supplied to DMA Channel 7. 190 (DMR0CR) (Address = 0x0106) Description Rabbit 4000 Microprocessor User’s Manual ...