20-668-0024 Rabbit Semiconductor, 20-668-0024 Datasheet - Page 322
20-668-0024
Manufacturer Part Number
20-668-0024
Description
IC CPU RABBIT4000 128-LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0024.pdf
(358 pages)
Specifications of 20-668-0024
Processor Type
Rabbit 4000 8-bit
Speed
60MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
20-668-0022
316-1078
316-1078
Available stocks
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Manufacturer
Quantity
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Part Number:
20-668-0024
Manufacturer:
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All important signals on the Rabbit 4000 are output-synchronized with the internal clock.
The internal clock is closely synchronized with the external clock, which is available on
the CLK pin. The delay in signal output depends on the capacitive load on the output lines.
In the case of the address lines, which are critically important for establishing memory
access time requirements, the capacitive loading is usually in the range of 25–100 pF, and
the load is due to the input capacitance of the memory devices and PC trace capacitance.
Delays are expressed from the waveform midpoint in keeping with the convention used by
memory manufacturers.
Table 28-9 lists the delays in gross memory access time for several values of VDD
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened or lengthened by a maximum amount given in the table above. The shortening
takes place by shortening the high part of the clock. If the doubler is not enabled, then
every clock is shortened during the low part of the clock period. The maximum shortening
for a pair of clocks combined is shown in the table.
The gross memory access time is 2T, where T is the clock period. To calculate the actual
memory access time, subtract the clock to address output time, the data in setup time, and
the clock period shortening due to the clock spectrum spreader from 2T.
Example Memory Access Time Calculation
• clock = 29.49 MHz, so T = 34 ns
• operating voltage is 3.3 V
• bus loading is 60 pF
• clock to address output delay = 8 ns (see Table 28-9)
• data setup time = 1 ns
• spectrum spreader is on in 1 ns mode, resulting in a loss of 3 ns worst-case (see
The access time is given by
312
VDD
Table 28-9)
(V)
3.3
1.8
IO
30 pF 60 pF 90 pF
Clock to Address
18
6
access time
Output Delay
Table 28-9. Preliminary Data and Clock Delays
(ns)
24
8
(V
11
33
DD
= 2T - (clock to address) - (data setup) - (spreader delay)
= 68 ns - 8 ns - 1 ns - 3 ns
= 56 ns
±10%, Temp. -40
Data Setup
Time Delay
(ns)
1
3
0.5 ns setting
no dbl / dbl
°
2.3 / 2.3
C to 85
Rabbit 4000 Microprocessor User’s Manual
7 / 6.5
Spectrum Spreader Delay
°
C)
Worst-Case
1 ns setting
no dbl / dbl
3 / 4.5
8 / 12
(ns)
2 ns setting
no dbl / dbl
11 / 22
4.5 / 9
IO
.
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