IDT79RC32H434-266BC IDT, Integrated Device Technology Inc, IDT79RC32H434-266BC Datasheet - Page 5

• Manufacturer Part Number: IDT79RC32H434-266BC
• Description: IC MPU 32BIT CORE 266MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-266BC

• Processor Type: MIPS32 32-Bit
• Speed: 266MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32H434-266BC

IDT RC32434
DDRCKP
DDRCSN
DDRDATA[15:0]
DDRDM[1:0]
DDRDQS[1:0]
DDRRASN
DDRVREF
DDRWEN
PCI Bus
PCIAD[31:0]
PCICBEN[3:0]
PCICLK
PCIDEVSELN
PCIFRAMEN
PCIGNTN[3:0]
PCIIRDYN
Signal
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
DDR Positive DDR clock. This signal is the positive clock of the differential
DDR clock pair.
DDR Chip Selects. This active low signal is used to select DDR device(s) on
the DDR bus.
DDR Data Bus. 16-bit DDR data bus is used to transfer data between the
RC32434 and the DDR devices. Data is transferred on both edges of the clock.
DDR Data Write Enables. Byte data write enables are used to enable specific
byte lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDR Data Strobes. DDR byte data strobes are used to clock data between
DDR devices and the RC32434. These strobes are inputs during DDR reads
and outputs during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0]
DDRDQS[1] corresponds to DDRDATA[15:8]
DDR Row Address Strobe. The DDR row address strobe is asserted during
DDR transactions.
DDR Voltage Reference. SSTL_2 DDR voltage reference is generated by an
external source.
DDR Write Enable. DDR write enable is asserted during DDR write transac-
tions.
PCI Multiplexed Address/Data Bus. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
PCI Multiplexed Command/Byte Enable Bus. PCI commands are driven by
the bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
PCI Clock. Clock used for all PCI bus transactions.
PCI Device Select. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32434
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32434 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32434 that access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
PCI Initiator Ready. Driven by the bus master to indicate that the current datum
can complete.
Table 1 Pin Description (Part 2 of 6)
5 of 53
Name/Description
January 19, 2006