IDT79RC32K438-300BBG IDT, Integrated Device Technology Inc, IDT79RC32K438-300BBG Datasheet - Page 4

• Manufacturer Part Number: IDT79RC32K438-300BBG
• Description: IC MPU 32BIT CORE 300MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-300BBG

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32K438-300BBG

Pin Description Table
(low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
IDT 79RC32438
The following table lists the functions of the pins provided on the RC32438. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
System
CLK
EXTCLK
COLDRSTN
RSTN
Memory and Peripheral Bus
BDIRN
BGN
BOEN
BRN
BWEN[1:0]
CSN[5:0]
MADDR[21:0]
MDATA[15:0]
OEN
RWN
Signal
Type
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
Master Clock. This is the master clock input. The processor frequency is a mul-
tiple of this clock frequency. This clock is used as the system clock for all mem-
ory and peripheral bus operations.
External Clock. This clock is used for all memory and peripheral bus opera-
tions.
Cold Reset. The assertion of this signal initiates a cold reset. This causes the
processor state to be initialized, boot configuration to be loaded, and the internal
PLL to lock onto the master clock (CLK).
Reset. The assertion of this bidirectional signal initiates a warm reset. This sig-
nal is asserted by the RC32438 during a warm reset.
External Buffer Direction. Memory and peripheral bus external data bus buffer
direction control. If the RC32438 memory and peripheral bus is connected to the
A side of a transceiver, such as an IDT74FCT245, then this pin may be directly
connected to the direction control (e.g., BDIR) pin of the transceiver.
Bus Grant. This signal is asserted by the RC32438 to indicate that the
RC32438 has relinquished ownership of the memory and peripheral bus.
External Buffer Enable. This signal provides an output enable control for an
external buffer on the memory and peripheral data bus.
Bus Request. This signal is asserted by an external device to request owner-
ship of the memory and peripheral bus.
Byte Write Enables. These signals are memory and peripheral bus byte write
enable signals.
BWEN[0] corresponds to byte lane MDATA[7:0]
BWEN[1] corresponds to byte lane MDATA[15:8]
Chip Selects. These signals are used to select an external device on the mem-
ory and peripheral bus.
Address Bus. 22-bit memory and peripheral bus address bus.
MADDR[25:22] are available as GPIO alternate functions
Data Bus. 16-bit memory and peripheral data bus. During a cold reset, these
pins function as inputs that are used to load the boot configuration vector.
Output Enable. This signal is asserted when data should be driven on by an
external device on the memory and peripheral bus.
Read Write. This signal indicates if the transaction on the memory and periph-
eral bus is a read transaction or a write transaction. A high level indicates a read
from an external device. A low level indicates a write to an external device.
Table 1 Pin Description (Part 1 of 9)
4 of 59
Name/Description
May 25, 2004