PCX745BVZFU350LE Atmel, PCX745BVZFU350LE Datasheet - Page 4

• Manufacturer Part Number: PCX745BVZFU350LE
• Description: IC MPU 32BIT 350MHZ 255PBGA
• Manufacturer: Atmel

Specifications of PCX745BVZFU350LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 350MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 255-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

4
PC755/745
• Fixed Point Units (FXUs) that share 32 GPRs for Integer Operands
• Floating-point Unit and a 32-entry FPR File
• System Unit
• Load/Store Unit
• Level 2 (L2) Cache Interface (not implemented on PC745)
– Fixed Point Unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical
– Fixed Point Unit 2 (FXU2)-shift, rotate, arithmetic, logical
– Single-cycle arithmetic, shifts, rotates, logical
– Multiply and divide support (multi-cycle)
– Early out multiply
– Support for IEEE-754 standard single and double precision floating point arithmetic
– Hardware support for divide
– Hardware support for denormalized numbers
– Single-entry reservation station
– Supports non-IEEE mode for time-critical operations
– Executes CR logical instructions and miscellaneous system instructions
– Special register transfer instructions
– One cycle load or store cache access (byte, half-word, word, double-word)
– Effective address generation
– Hits under misses (one outstanding miss)
– Single-cycle unaligned access within double word boundary
– Alignment, zero padding, sign extend for integer register file
– Floating point internal format conversion (alignment, normalization)
– Sequencing for load/store multiples and string operations
– Store gathering
– Cache and TLB instructions
– Big and Little-endian byte addressing supported
– Misaligned Little-endian supported
– Level 1 Cache structure
– 32K, 32 bytes line, 8-way set associative instruction cache (iL1)
– 32K, 32 bytes line, 8-way set associative data cache (dL1)
– Cache locking for both instruction and data caches, selectable by group of ways
– Single-cycle cache access
– Pseudo least-recently used (PLRU) replacement
– Copy-back or Write Through data cache (on a page per page basis)
– Supports all PowerPC memory coherency modes
– Non-Blocking instruction and data cache (one outstanding miss under hits)
– No snooping of instruction cache
– Internal L2 cache controller and tags; external data SRAMs
– 256K, 512K, and 1-Mbyte 2-way set associative L2 cache support
2138G–HIREL–05/06