TS68020VR16 Atmel, TS68020VR16 Datasheet

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... Screening/Quality This product is manufactured in full compliance with either: • MIL-STD-883 (class B) • DESC 5962 - 860320 • or according to Atmel standards See “Ordering Information” on page 43. Pin connection: see page 3. R suffix PGA 114 Ceramic Pin Grid Array F suffix CQFP 132 Ceramic Quad Flat Pack ...

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Introduction Figure 1. TS68020 Block Diagram TS68020 2 The TS68020 is a high-performance 32-bit microprocessor the first microprocessor to have evolved from a 16-bit machine to a full 32-bit machine that provides 32-bit address and data buses as ...

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The micromachine consists of an execution unit, nanorom and microrom storage, an instruction decoder, an instruction pipe, and associated control sections. The execution unit consists of an address section, an operand address section, and a data section. Microcode control ...

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Figure 4. Functional Signal Groups Signal Description Group Address Bus Data Bus Logic Clock TS68020 4 Figure 4 illustrates the functional signal groups and Table 1 lists the signals and their function. The V and GND pins are separated into ...

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Table 1. Signal Index Signal Name Mnemonic Address Bus A0-A31 Data Bus D0-D31 Function Codes FC0-FC2 Size SIZ0/SIZ1 Read-Modify-Write Cycle RMC External Cycle Start ECS Operand Cycle Start OCS Address Strobe AS Data Strobe DS Read/Write R/W Data Buffer Enable ...

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Detailed Specifications Scope Applicable Documents MIL-STD-883 Requirements General Design and Construction Terminal Connections Lead Material and Finish Package TS68020 6 This drawing describes the specific requirements for the microprocessor 68020, 16.67 MHz, 20 MHz and 25 MHz, in compliance with ...

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Electrical Characteristics Table 2. Absolute Maximum Ratings Symbol Parameter V Supply Voltage CC V Input Voltage I P Max Power Dissipation dmax T Operating Temperature case T Storage Temperature stg T Lead Temperature leads Table 3. Recommended Condition of Use ...

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Table 4. Thermal Characteristics at 25°C Package Symbol Parameter θ Thermal Resistance - Ceramic Junction to Ambient JA PGA 114 θ Thermal Resistance - Ceramic Junction to Case JC θ Thermal Resistance - Ceramic Junction to Ambient JA CQFP 132 ...

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... B devices. The document where are defined the marking are identified in the related reference doc- uments. Each microcircuit are legible and permanently marked with the following information as minimum: • ATMEL Logo • Manufacturer’s Part Number • Class B Identification • ...

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Table 5. Static Characteristics Symbol Parameter I Maximum Supply Current CC I Maximum Supply Current CC V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Output Voltage OH All Outputs V Low ...

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Dynamic (Switching) Characteristics Table 6. Dynamic Electrical Characteristics Symbol Parameter t Clock Pulse Width CPW t Clock High to Address/FC/Size/RMC CHAV Valid t Clock High to ECS, OCS Asserted CHEV t Clock High to Address/Data/FC/RMC/ CHAZX Size High Impedance t ...

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Table 6. Dynamic Electrical Characteristics (Continued) Symbol Parameter t Data Out Valid to DS Asserted (Write) DVSA 26 t Data in Valid to Clock Low (Data Setup) DICL t Late BERR/HALT Asserted to Clock BELCL Low Setup Time t AS, ...

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Table 6. Dynamic Electrical Characteristics (Continued) Symbol Parameter f Frequency of Operation t R/W Asserted to Data Bus Impedance RADC Change t RESET Pulse Width (Reset Instruction) HRPW t BERR Negated to HALT Negated BNHN (Rerun) t BGACK Negated to ...

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Test Conditions Specific to the Device Loading Network Table 7. Load Network Load NBR Figure 1. 0.74 k Note: 1. Equivalent loading may be simulated by the tester. TS68020 14 The applicable loading ...

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Time Definitions Figure 9. Read Cycle Timing Diagram Note: Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and ...

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Figure 10. Write Cycle Timing Diagram (Continued) Note: Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing thorough this range should start outside and pass ...

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Figure 11. Bus Arbitration Timing Diagram Note: Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing thorough this range should start outside and pass through ...

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... TS68020 clock input and, possibly, relative to one or more other signals. The measurement of the AC specifications is defined by the waveforms in Figure 12. In order to test the parameters guaranteed by Atmel, inputs must be driven to the voltage levels specified in Figure 12. Outputs of the TS68020 are specified with minimum and/or maximum limits, as appropriate, and are measured as shown ...

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Figure 12. Drive Levels and Test Points for AC Specification Legend: A) Maximum Output Delay Specification B) Minimum Output Hold Time C) Minimum Input Setup Time Specification D) Minimum Input Hold Time Specification E) Signal Valid to Signal Valid Specification ...

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Additional Information Power Consideration Capacitance (Not for Inspection Purposes Capacitance Derating Curves TS68020 20 Additional information shall not be for any inspection purposes. See Table 4. ) Symbol Parameter Test Conditions Input Capacitance ...

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Figure 14. ECS and OCS Capacitance Derating Curve Figure 15. R/W, FC, SIZ0-SIZ1, and RMC Capacitance Derating Curve TS68020 21 ...

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TS68020 22 Figure 16. DS, AS, IPEND, and BG Capacitance Derating Curve Figure 17. DBEN Capacitance Derating Curve 2115A–HIREL–07/02 ...

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Functional Description Description of Registers 2115A–HIREL–07/02 Figure 18. Data Capacitance Derating Curve As shown in the programming models (Figure 19 and Figure 20) the TS68020 has six- teen 32-bit general-purpose registers, a 32-bit program counter, two 32-bit supervisor stack pointers, ...

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Figure 19. User Programming Model TS68020 24 The TS68000 Family processors distinguish address spaces as supervisor / used and program/data. These four combinations are specified by the function code pins (FC0/FC1/FC2) during bus cycles, indication the particular address space. Using ...

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Figure 20. Supervisor Programming Model Supplement Figure 21. Status Register Data Types and Addressing Modes 2115A–HIREL–07/02 Seven basic types are supported. These data types are: • Bits • Bits Flieds (String of consecutive bits, 1-32 bits long) • BCD Digits ...

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Table 8. TS68020 Addressing Modes Addressing Modes Register Direct Data Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect with Post Increment Address Register Indirect with Predecrement Address Register Indirect with Displacement Register Indirect with Index ...

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Table 8. TS68020 Addressing Modes (Continued) Addressing Modes Absolute Absolute Short Absolute Long Immediate Notes Data Register, D0-D7 Address Register, A0-A7 twos-complement, or sign—extended displacement; added as part ...

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Instruction Set Overview TS68020 28 The TS68020 instruction set is shown in Table 9. Special emphasis has been given to the instruction set’s support of structured high-level languages and sophisticated operat- ing systems. Each instruction, with few exceptions, operates on ...

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Table 9. Instruction Set (Continued) Mnemonic CALLM CAS CAS2 CHK CHK2 CLR CMP CMPA CMPI CMPM CMP2 DBcc DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB ILLEGAL JMP JSR LEA LINK LSL, LSR MOVE MOVEA MOVE CCR MOVE ...

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TS68020 30 Table 9. Instruction Set (Continued) Mnemonic OR ORI PACK PEA RESET ROL, ROR ROXL, ROXR RTD RTE RTM RTR RTS SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST UNLK UNPK Co-processor Instructions ...

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Bit Field Operation Binary Coded Decimal (BCD) Support Bounds Checking System Traps 2115A–HIREL–07/02 The TS68020 supports variable length bit field operations up to 32-bit. A bit field may start in any bit position and span any address boundary for the ...

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Multi-processing Module Support Virtual Memory/Machine Concepts Virtual Memory TS68020 32 To further support multi-processing with the TS68020, a compare and swap instruction, CAS, has been added. This instruction makes use of the read-modify-write cycle to compare two operands and swap ...

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Virtual Machine Operand Transfer Mechanism 2115A–HIREL–07/02 The TS68020 uses instruction continuation to support virtual memory. In order for the TS68020 to use instruction continuation, it stores its internal state on the supervisor stack when a bus cycle is terminated with ...

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The Co-processor Concept TS68020 34 The TS68020 will always transfer the maximum amount of data on all bus cycles; i.e., it always assumes the port is 32-bit wide when beginning the bus cycle. In addition, the TS68020 has no restrictions ...

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Other microprocessors in the TS68000 Family can operate any TS68000 co-processor even though they may not have the hardware implementation of the co-processor inter- face as does the TS68020. Since the co-processor is operated through the co- processor interface ...

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Co-processor Protocol TS68020 36 Table 11. Co-processor Primitives (Continued) General Operand Transfer Evaluate and Pass (Ea.) Evaluate (Ea.) and Transfer Data Write to Previously Evaluated (Ea.) Take Address and Transfer Data Transfer to/from Top of Stack Register Transfer Transfer CPU ...

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Primitives/Response Exceptions Kinds of Exceptions Exception Processing Sequence 2115A–HIREL–07/02 When the main processor encounters the next co-processor instruction, the main pro- cessor queries the co-processor until the co-processor is ready; meanwhile, the main processor can service interrupts ...

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On-chip Instruction Cache TS68020 Cache Goals TS68020 38 The TS68020 provides an extension to the exception stacking process. If the M bit in the status register is set, the master stack pointer (MSP) is used for all task related excep- ...

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Figure 22. TS68020 On-chip Cache Organization 2115A–HIREL–07/02 Second, and probably the most important benefit of the cache, is that it allows instruc- tion stream fetches and operand accesses to proceed in parallel. For example, if the TS68020 requires both an ...

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... Handling TS68020 40 Atmel offers a certificate of compliance with each shipment of parts, affirming the prod- ucts are in compliance with MIL-STD-883 and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range. MOS devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge ...

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Package Mechanical Data Figure 23. 114-lead - Ceramic Pin Grid Array Figure 24. 132 Pins - Ceramic Quad Flat Pack 2115A–HIREL–07/02 TS68020 41 ...

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Mass Terminal Connections 114-lead - Ceramic Pin Grid Array 132-lead - Ceramic Quad Flat Pack TS68020 42 PGA 114 - 6 grams typically CQFP 132 - 14 grams typically See Figure 2. See Figure 3. 2115A–HIREL–07/02 ...

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... TS68020DESC02XA TS68020DESC03XA TS68020DESC04XA TS68020DESC02XC TS68020DESC03XC TS68020DESC04XC TS68020DESC02YA TS68020DESC03YA TS68020DESC04YA TS68020DESC02YC TS68020DESC03YC TS68020DESC04YC Standard Product Commercial Atmel Part-Number TS68020VR16 TS68020VR20 TS68020VR25 TS68020MR16 TS68020MR20 TS68020MR25 2115A–HIREL–07/02 Temperature Range Package PGA 114 PGA 114/tin PGA 114 PGA 114/tin PGA 114 PGA 114/tin ...

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... TS68020MF20 TS68020MF25 Device Type Temperature range M: -55, +125°C V: -40, +85 Package R = Pin grid array 114 F = CQFP 132 Note: For availability of the different versions, contact your Atmel sales office. TS68020 44 Norms Package Internal Standard CQFP 132 Internal Standard CQFP 132 Internal Standard ...

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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...