TS68040VR33A Atmel, TS68040VR33A Datasheet - Page 37

• Manufacturer Part Number: TS68040VR33A
• Description: IC MPU 32BIT 33MHZ 179PGA
• Manufacturer: Atmel

Specifications of TS68040VR33A

• Processor Type: 68000 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Instruction and Data
Caches
Cache Organization
2116A–HIREL–09/02
Studies have shown that typical programs spend much of their execution time in a few
main routines or tight loops. Earlier members of the TS68000 Family took advantage of
this locality of reference phenomenon to varying degrees. The TS68040 takes further
advantage of cache technology with its two, independent, on-chip, physical address
space caches, one for instructions and one for data. The caches reduce the processor’s
external bus activity and increase CPU throughput by lowering the effective memory
access time. For a typical system design, the large caches of the TS68040 yield a very
high hit rate, providing a substantial increase in system performance. Additionally, the
caches are automatically burstfilled from the external bus whenever a cache miss
occurs.
The autonomous nature of the caches allows instruction-stream fetches, data-stream
fetches, and a third external access to occur simultaneously with instruction execution.
For example, if the TS68040 requires both an instruction-stream access and an external
peripheral access and if the instruction is resident in the on-chip cache, the peripheral
access proceeds unimpeded rather than being queued behind the instruction fetch. If a
data operand is also required and if it is resident in the data cache, it can also be
accessed without hindering either the instruction access from its cache or the peripheral
access external to the chip. The parallelism inherent in the TS68040 also allows multiple
instructions that do not require any external accesses to execute concurrently while the
processor is performing an external access for a previous instruction.
The instruction and data caches are four-way set-associative with 64 sets of four, 16-
byte lines for a total cache storage of 4K bytes each. As shown in Figure 21, each 16-
byte line contains an address tag and state information. State information for each entry
consists of a valid flag for the entire line in both instruction and data caches and write
status for each long word in the data cache. The write status in the data cache signifies
whether or not the long-word data is dirty (meaning that the data in the cache has been
modified but has not been written back to external memory) for data in copyback pages.
TS68040
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