TS68040 ATMEL Corporation, TS68040 Datasheet
TS68040
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TS68040 Summary of contents
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DESCRIPTION The TS 68040 is Thomson’s third generation of 68000-com- patible, high-performance, 32-bit microprocessors. The TS 68040 is a virtual memory microprocessor employing mul- tiple, concurrent execution units and a highly integrated archi- tecture to provide very high performance in ...
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SUMMARY A - GENERAL DESCRIPTION 1 - INTRODUCTION 2 - PIN ASSIGNMENTS 2.1 - PGA 179 2.2 - CQFP 196 3 - SIGNAL DESCRIPTION 2/ DETAILED SPECIFICATIONS 1 - SCOPE 2 - APPLICABLE DOCUMENTS 3 - REQUIREMENTS 3.1 ...
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A - GENERAL DESCRIPTION 1 - INTRODUCTION The TS 68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the integer unit processing capabilities of the TS 68030 microprocessor with independent 4K-byte data and instruction caches and an on-chip FPU. The ...
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PIN ASSIGNMENTS 2.1 - PGA 179 Table 1 PLL Internal logic Output drivers 4/38 Figure 2 : Bottom view. GND C6, C7, C9, C11, C13, K3, K16, L3, M16, R4, R11, R13, S10, T4, S9, R6, R10 B2, ...
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CQFP 196 Table 2 PLL Internal logic Output drivers Figure 3 : Pin assignments. GND 4, 9, 10, 19, 32, 45, 73, 88, 113, 119, 121, 122, 124, 125, 129, 130, 141, 159, 172 7, 15, 22, 28, ...
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SIGNAL DESCRIPTION Figure 4 and Table 3 describe the signals on the TS 68040 and indicate signal functions. The test signals, TRST, TMS, TCK, TDI, and TDO, comply with subset P-1149.1 of the IEEE testability bus standard. 6/38 ...
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Table 3 - Signal index Signal Name Address bus Data bus Transfer type Transfer modifier Transfer line number User programmable attributes Read write Transfer size Bus lock Bus lock end Cache inhibit out Transfer start Transfer in progress Transfer acknowledge ...
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Table 3 - Signal index (Continued) Signal Name Processor clock Test clock Test mode select Test data input Test data output Test reset Power supply Ground B - DETAILED SPECIFICATIONS 1 - SCOPE This drawing describes the specific requirements for ...
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Table 4 - Absolute maximum ratings Symbol V CC Supply voltage range V I Input voltage range P D Power dissipation T C Operating temperature T stg Storage temperature range T J Junction temperature (see Note) T lead Lead temperature ...
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Thermal device characteristics The TS 68040 presents some inherent characteristics which should be considered when evaluating a method of cooling the device. The following paragraphs discuss these die / package and power considerations. Die and package The TS 68040 is ...
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Relationships between thermal resistances and temperatures Since the maximum operating junction temperature has been specified to be 125°C. The maximum case temperature °C can be obtained from : where : Maximum case temperature ...
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Table 8 - Thermal parameters with forced air flow and no heat sink Thermal Mgmt. Defined parameters Technique P D Air-flow velocity 100 LFM 3 W 250 LFM 3 W 500 LFM 3 W 750 LFM 000 ...
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All pin fin heat sinks tested were made from extrusion Al products. The planar face of the heat sink mating to the package should have a good degree of planarity ; if it has any curvature, the curvature should be ...
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Table 10 - Thermal parameters with heat sink and air-flow Thermal Mgmt. Technique P D Air-flow Heat sink 100 LFM 2338B 3 W 250 LFM 2338B 3 W 500 LFM 2338B 3 W 750 LFM 2338B 000 ...
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Mechanical and environment The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or for TCS standard screening. 3.6 - Marking The document where are defined the marking are identified in the related ...
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Table 12 - Electrical characteristics (Continued) Symbol V OL Output low voltage Larger buffers - I Small buffers - Power dissipation (T Larger buffers enabled Small buffers enabled Capacitance - Note ...
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Table 14 - Output AC timing specifications (Note 1) (Figures 9 - 15) These output specifications are for only 25 MHz they must be scaled for lower operating frequencies. Refer to TS 6804DH/AD for further information. – 55° ...
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Table 14 - Output AC timing specifications (Continued) Num Characteristic 43 BCLK to MI valid 48 BCLK to TA valid 50 BCLK to IPEND, PSTn, RSTO valid Note 1 : Output timing is specified for a valid signal measured at ...
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Table 15 - Input AC timing specifications (Figures 9 - 15) – 55° 4. Jmax Num 15 Data-in valid to BCLK (setup) 16 BCLK to data-in invalid (hold) 17 BCLK to data-in high ...
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Note : Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT Table 16 - JTAG timing application (Figures 16 - 19) – 55° 4. Jmax Num TCK frequency 1 TCK ...
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Table 17 - Boundry scan instruction codes Bit 2 Bit 5.4 - Switching test circuit and waveforms Figure 10 : Address and data ...
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Figure 12 : Bus arbitation timing. Figure 13 : Snoop hit timing. ...
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Figure 14 : Snoop miss timing. Figure 15 : Other signal timing. 23/38 ...
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Figure 16 : Clock input timing diagram. Figure 17 : TRST timing diagram. Figure 18 : Boundry scan timing diagram. Figure 19 : Test access port timing diagram. ...
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FUNCTIONAL DESCRIPTION 6.1 - Programming model The TS 68040 integrates the functions of the integer unit, MMU, and FPU. As shown in Figure 20, the registers depicted in the programming model provide access and control for the three ...
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Data types and addressing modes The TS 68040 supports the basic data types shown in Table 18. Some data types apply only to the integer unit, some only to the FPU, and some to both the integer unit ...
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Single- and double-precision floating-point data formats are implemented in the FPU as defined by the IEEE standard. These data formats are the main floating-point formats and should be used for most calculations involving real numbers. The extended-precision data format is ...
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Instruction set overview The instruction provided by the TS 68040 are listed in Table 20. The instruction set has been tailored to support high-level languages and is optimized for those instructions most commonly executed (however, all instructions listed ...
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Table 21 - Floating-point instructions Mnemonic Description *FABS Floating-point absolute value *FADD Floating-point add *FBcc Branch on floating-point condition *FCMP Floating-point compare *FDBcc Floating-point decrement and branch *FDIV Floating-point divide *FMOVE Move floating-point register *FMOVEM Move multiple floating-point registers Floating-point ...
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The caches are accessed by physical addresses from the on-chip MMUs. The translation of the upper bits of the logical address occurs concurrently with the accesses into the set array in the cache by the lower address bits. The output ...
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Cache instructions The TS 68040 supports the following instructions for cache maintenance. Both instructions may selectively operate on the data or instruction cache. CINV : Invalidates a single line, all lines in a physical page, or the entire ...
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Translation mechanism Because logical-to-physical address translation is one of the most frequently executed operations of the TS 68040 MMUs, this task has been optimized. Each MMU initiates address translation by searching for a descriptor containing the address translation ...
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Transparent translation Four transparent translation registers, two each for instruction and data accesses, have been provided on the TS 68040 MMU to allow portions of the logical address space to be transparently mapped and accessed without the need ...
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Tie bar CQFP cavity up (on request) 34/38 Dim Millimeters Inches A 3.30 max 0.130 max 0.05 .002 B 0.23 .009 – – 0.038 .015 C 0.635 typ. .025 typ. 33.91 0.25 1.335 .01 D1 ...
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Gullwing CQFP cavity up * Reduced pin count shown for clarity, 49 pins per side Symbol Millimeters Inches A 4.19 max 0.165 max 0.673 0.2 .0265 .008 A1 0.05 b 0.23 .009 – – 0.038 ...
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ORDERING INFORMATION 10.1 - MIL-STD-883 C and internal standard Note 1 : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Note request. Note 3 : Standard process. Note request for small quantity. 10.2 - DESC ...
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... DESC TS68040DESC02ZA DESC TS68040DESC02ZC DESC TS68040MFB/C25 MIL-STD-883 TS68040MFB/C33 MIL-STD-883 TS68040MRD/T25 BURN IN TS68040MRD/T33 BURN IN TS68040MFD/T25 BURN IN TS68040MFD/T33 BURN IN Note : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. 10.3.2 - Standard product Commercial TCS part number Norms (see Note) TS68040VR25 TCS standard TS68040VR33 TCS standard TS68040MR25 TCS standard TS68040MR33 TCS standard ...
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TS 68040 Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may ...